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document number: 311826-002 intel ? celeron ? d processor 300 sequence datasheet ? on 65 nm process in the 775-land package september 2006
2 datasheet information in this document is provided in connection with in tel products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or ch aracteristics of any features or instructio ns marked "reserved" or "undefined." int el reserves these for future definition and shall have no respon sibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? celeron ? d processor on 65 nm process may contain design defects or erro rs known as errata which may cause the product to deviate from published specifications. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. over time processor numbers will increment ba sed on changes in clock speed, cache, fsb, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. current roadmap processor number progre ssion is not necessarily representative of future roadmaps. see http://www.intel.com/products/processor_numbe r for details. intel ? 64 requires a computer system with a processor, chipset, bios , operating system, device drivers, and applications enabled for intel 64. processor will not operate (including 32-bit operation) without an intel 64-enabled bios. performance will vary depending on yo ur hardware and software configurations. see http://www.intel.com/info/em64t for more information including details on which processors support intel 64, or consult with your system vendor for more information. enabling execute disable bit functionality requires a pc with a processor with execute disable bit capability and a supporting operating system. check with your pc manufacturer on whether your system delivers execute disable bit functionality. intel, pentium, celeron, and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2006 intel corporation.
datasheet 3 contents 1 introduction................................................................................................................. 9 1.1 terminology ....................................................................................................... 9 1.1.1 processor packaging terminology ............................................................. 10 1.2 references ....................................................................................................... 11 2 electrical specifications ............................................................................................... 13 2.1 power and ground lands.................................................................................... 13 2.2 decoupling guidelines ........................................................................................ 13 2.2.1 vcc decoupling ..................................................................................... 13 2.2.2 vtt decoupling ...................................................................................... 14 2.2.3 fsb decoupling...................................................................................... 14 2.3 voltage identification ......................................................................................... 14 2.4 reserved, unused, and testhi signals ................................................................ 16 2.5 voltage and current specification ................. ....................................................... 17 2.5.1 absolute maximum and minimum ratings ..... ............................................. 17 2.5.2 dc voltage and current specification ........................................................ 18 2.5.3 vcc overshoot ...................................................................................... 21 2.5.4 die voltage validation ............................................................................. 22 2.6 signaling specifications...................................................................................... 22 2.6.1 fsb signal groups.................................................................................. 23 2.6.2 gtl+ asynchronous signals..................................................................... 25 2.6.3 processor dc specifications ..................................................................... 25 2.6.3.1 gtl+ front side bus specifications ............................................. 28 2.7 clock specifications ........................................................................................... 29 2.7.1 front side bus clock (bclk[1:0]) and processor clocking ............................ 29 2.7.2 fsb frequency select signals (bsel[2:0])................................................. 29 2.7.3 phase lock loop (pll) and filter .............................................................. 30 2.7.4 bclk[1:0] specifications ......................................................................... 32 3 package mechanical specifications ....................... ......................................................... 33 3.1 package mechanical drawing........................ ....................................................... 33 3.2 processor component keep-out zones ................................................................. 37 3.3 package loading specifications ........................................................................... 37 3.4 package handling guidelines............................................................................... 37 3.5 package insertion specifications.......................................................................... 38 3.6 processor mass specification ............................................................................... 38 3.7 processor materials............................................................................................ 38 3.8 processor markings............................................................................................ 38 3.9 processor land coordinates ................................................................................ 39 4 land listing and signal descriptions .................... ......................................................... 41 4.1 processor land assignments ............................................................................... 41 4.2 alphabetical signals reference ............................................................................ 64 5 thermal specifications and design considerations.... ....................................................... 75 5.1 processor thermal specifications ......................................................................... 75 5.1.1 thermal specifications ............................................................................ 75 5.1.2 thermal metrology ................................................................................. 79 5.2 processor thermal features ................................................................................ 79 5.2.1 thermal monitor..................................................................................... 79 5.2.2 on-demand mode .................................................................................. 80 5.2.3 prochot# signal .................................................................................. 81 5.2.4 thermtrip# signal ............................................................................... 81
4 datasheet 5.2.5 t control and fan speed reduction ...........................................................81 5.2.6 thermal diode........................................................................................81 6 features ....................................................................................................................85 6.1 power-on configuration options ..........................................................................85 6.2 clock control and low power states .....................................................................85 6.2.1 normal state .........................................................................................86 6.2.2 halt and enhanced halt powerdown states..............................................86 6.2.2.1 halt powerdown state ..............................................................87 6.2.2.2 enhanced halt powerdown state................................................87 6.2.3 stop grant state ....................................................................................87 6.2.4 enhanced halt snoop or halt snoop state, stop grant snoop state...........................................................................88 6.2.4.1 halt snoop state, stop grant snoop state ..................................88 6.2.4.2 enhanced halt snoop state .......................................................88 7 boxed processor specifications .....................................................................................89 7.1 mechanical specifications ............................. .......................................................89 7.1.1 boxed processor cooling solution dimensions.............................................89 7.1.2 boxed processor fan heatsink weight .......................................................91 7.1.3 boxed processor retention mechanism and heatsink attach clip assembly...............................................................................91 7.2 electrical requirements ......................................................................................91 7.2.1 fan heatsink power supply ......................................................................91 7.3 thermal specifications........................................................................................93 7.3.1 boxed processor cooling requirements......................................................93 8 debug tools specifications ...........................................................................................95 8.1 logic analyzer interface (lai) .............................................................................95 8.1.1 mechanical considerations ..................... ..................................................95 8.1.2 electrical considerations ........................ ..................................................95
datasheet 5 figures 1v cc static and transient tolerance for 775_vr_config_05a and 775_vr_config_06 processors................................................................................. 21 2v cc overshoot example waveform ............................................................................. 22 3 phase lock loop (pll) filter requirements .................................................................. 31 4 processor package assembly sketch ........................................................................... 33 5 processor package drawing (sheet 1 of 3)................................................................... 34 6 processor package drawing sheet 2 of 3 ..................................................................... 35 7 processor package drawing sheet 3 of 3 ..................................................................... 36 8 processor top-side marking example .......................................................................... 38 9 processor land coordinates and quadrants (top view ) ................................................. 39 10 land-out diagram (top view ? left side) ..................................................................... 42 11 land-out diagram (top view ? right side) ................................................................... 43 12 thermal profile for 775_vr_config_05a processors .................................................... 77 13 thermal profile for 775_vr_config_06 processors ...................................................... 78 14 case temperature (tc) measurement location ........ .................................................... 79 15 processor low power state machine ........................................................................... 86 16 mechanical representation of the boxed processor ....................................................... 89 17 space requirements for the boxed processor (side view: applies to all four side views) ............................................................................................... 90 18 space requirements for the boxed processor (top view)............................................... 90 19 space requirements for the boxed processor (ove rall view) ......................................... 91 20 boxed processor fan heatsink power cable connector description .................................. 92 21 baseboard power header placement relative to pr ocessor socket ................................... 93 22 boxed processor fan heatsink airspace keep-out requirements (side 1 view) .......................................................................................................... 94 23 boxed processor fan heatsink airspace keep-out requirements (side 2 view) .......................................................................................................... 94
6 datasheet tables 1 references ..............................................................................................................11 2 voltage identification definition .... ..............................................................................15 3 absolute maximum and minimum ratings ............... .....................................................17 4 voltage and current specifications..................... .........................................................18 5 vcc static and transient tolerance for 775_vr_config_05a and 775_vr_config_06 processors .................................................................................20 6 vcc overshoot specifications......................................................................................21 7 fsb signal groups ....................................................................................................23 8 signal characteristics................................................................................................24 9 signal reference voltages .........................................................................................24 10 gtl+ signal group dc specifications ..........................................................................25 11 gtl+ asynchronous signal group dc specifications ......................................................26 12 pwrgood and tap signal group dc specifications.......................................................26 13 vttpwrgd dc specifications .....................................................................................27 14 bsel[2:0] and vid[5:0] dc specifications ...................................................................27 15 bootselect dc specifications ..................................................................................27 16 gtl+ bus voltage definitions .....................................................................................28 17 core frequency to fsb multiplier configuration.............................................................29 18 bsel[2:0] frequency table for bclk[1:0] ...................................................................30 19 front side bus differential bclk sp ecifications .............................................................32 20 processor loading specifications........................ .........................................................37 21 package handling guidelines......................................................................................37 22 processor materials ...................................................................................................38 23 alphabetical land assignments...................................................................................44 24 numerical land assignment .......................................................................................54 25 signal description (sheet 1 of 9) ................................................................................64 26 processor thermal specifications for 775_vr_co nfig_05a processors ............................76 27 processor thermal specifications for 775_vr_co nfig_06 processors ..............................76 28 thermal profile for 775_vr_config_05a processors.....................................................77 5-1 thermal profile for 775_vr_config_06 processors ......................................................78 29 thermal ?diode? parameters using diode model ............................................................82 30 thermal ?diode? parameters using transistor model . .....................................................82 31 thermal ?diode? n trim and diode_correction_offset.......................................................83 32 thermal diode interface ............................................................................................83 33 power-on configuration option signals .......................................................................85 34 fan heatsink power and signal specifications ........ .......................................................92
datasheet 7 revision history rev no. description date -001 ? initial release may 2006 -002 ? added 775_vr_config_06 specifications ? added celeron d processor 360 specifications september 2006
8 datasheet intel ? celeron ? d processor 300 sequence features the intel ? celeron ? d processor family expands intel?s processor family into the value-priced pc market segment. celeron d processors provide the value that offers the customer the capability to affordably get onto the internet, and use ed ucational programs, home-office software, and productivity applications. all of the celeron d processors include an integrated l2 cache, and are built on intel?s advanced cmos process technology. the ce leron d processor is backed by over 30 years of intel experience in manufacturing high-quality, reliable microprocessors. intel ? 64 enables celeron d processors to execute operating systems and applications written to take advantage of the intel 64. the celeron d processor also includes the execute di sable bit capability. this feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. ? available at 3.46 ghz, 3.33 ghz and 3.2 ghz ? supports intel ? 64 ? supports execute disable bit capability ? binary compatible with applications running on previous members of the intel microprocessor line ? intel netburst ? microarchitecture ? fsb frequency at 533 mhz ? hyper-pipelined technology ? advance dynamic execution ? very deep out-of-order execution ? enhanced branch prediction ? optimized for 32-bit applications running on advanced 32-bit operating systems ? 144 streaming simd extensions 2 (sse2) instructions ? 13 streaming simd extensions 3 (sse3) instructions ? two 16-kb level 1 data caches ? 256-kb advanced transfer cache (on-die, full-speed level 2 (l2) cache) with 8-way associativity and error correcting code (ecc) ? 8-way cache associativity provides improved cache hit rate on load/store operations ? enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3d performance ? power management capabilities ? system management mode ?multiple low-power states ? 775-land package
datasheet 9 introduction 1 introduction the intel ? celeron ? d processors 360, 356, and 352 are single-core desktop processors on the 65 nm process. the processor uses flip-chip land grid array (fc- lga6) package technology, and plugs into the lga775 socket. note: in this document the intel ? celeron ? d processor 300 sequence on the 65 nm process is referred to as the ?celeron d processor? or simply ?the processor.? note: in this document, unless othe rwise specified, the intel ? celeron ? d processor 300 sequence refers to intel celeron d processors 360, 356, and 352. the celeron d processor supports intel ? 64 as an enhancement to intel?s ia-32 architecture. this enhancement enables the processor to execute operating systems and applications written to take advantage of intel 64. further details on the 64-bit extension architecture and programming model can be found in the intel ? extended memory 64 technology software developer guide at http://developer.intel.com/ technology/64bitextensions/. the celeron d processor is based on the intel 32-bit microarchitecture and maintains the tradition of compatibility with ia-32 software. it has the front side bus (fsb) data transfer speed at 533 mb/s and level 2 cache size of 512 kb. the celeron d processor also includes the execute disable bit capability. this feature, combined with a supported operating syst em, allows memory to be marked as executable or non-executable. if code atte mpts to run in non-executable memory, the processor raises an error to the operating system. this feature can prevent some classes of viruses or worms that exploit bu ffer over run vulnerabilities and can, thus, help improve the overall secu rity of the system. see the intel ? architecture software developer's manual for more detailed information. intel will enable support components for th e celeron d processor including heatsink, heatsink retention mechanism, and socket. manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. the processor includes an address bus powe r down capability that removes power from the address and data signals when the fsb is not in use. this feature is always enabled on the processor. 1.1 terminology a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). ?front side bus? refers to the interface between the processor and system core logic (a.k.a. the chipset components ). the fsb is a multiprocessing interface to processors, memory, and i/o.
introduction 10 datasheet 1.1.1 processor packaging terminology commonly used terms are expl ained here for clarification: ? intel ? celeron ? d processor 300 sequence on 65 nm process in the 775- land package ? processor in the fc-lga6 package with a 512 kb l2 cache. ? processor ? for this document, the term processor is the generic form of the celeron d processor. ? keep-out zone ? the area on or near the processor that system design can not use. ?intel ? 945g/945gz/945p/945pl express chipset family ? chipset that supports ddr and ddr2 memory technology for the celeron d processor on 65 nm process. ? processor core ? processor core die with integrated l2 cache. ? lga775 socket ? the celeron d processor on 65 nm process mates with the system board through a surface mount, 775-land, lga socket. ? integrated heat spreader (ihs) ?a component of the processor package used to enhance the thermal performance of the package. component thermal solutions interface with the processor at the ihs surface. ? retention mechanism (rm) ? since the lga775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket. ? fsb (front side bus) ? the electrical interface that connects the processor to the chipset; also referred to as the proc essor system bus or the system bus. all memory and i/o transactions as well as interrupt messages pass between the processor and chipset over the fsb. ? storage conditions ? refers to a non-operational state. the processor may be installed in a platform, in a tray, or loose. processors may be sealed in packaging or exposed to free air. under these conditions, processor lands should not be connected to any supply voltages, have any i/os biased, or receive any clocks. upon exposure to ?free air?(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (msl) as indi cated on the packaging material. ? functional operation ? refers to normal operating conditions in which all processor specifications, including dc, ac, system bus, signal quality, mechanical and thermal are satisfied.
datasheet 11 introduction 1.2 references material and concepts available in the fo llowing documents may be beneficial when reading this document. table 1. references document location intel ? celeron ? d processor 300 sequen ce specification update intel ? pentium ? d processor 900 sequence, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines http://intel.com/design/ pentiumxe/designex/ 306830.htm voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket http://intel.com/design/ pentium4/guides/ 302356.htm lga775 socket mechanical design guide http://intel.com/design/ pentium4/guides/ 302666.htm ia-32 intel architecture so ftware developer's manual volume 1: basic architecture http://www.intel.com/ design/penti um4/manuals/ 253665 volume 2a: instructio n set reference, a-m http://www.intel.com/ design/penti um4/manuals/ 253666 volume 2b: instructio n set refere nce, n-z http://www.intel.com/ design/penti um4/manuals/ 253667 volume 3a: system programming guide http://www.intel.com/ design/penti um4/manuals/ 253668 volume 3b: system programming guide http://www.intel.com/ design/penti um4/manuals/ 253669
introduction 12 datasheet
datasheet 13 electrical specifications 2 electrical specifications this chapter describes the electrical charac teristics of the processor interfaces and signals. dc electrical characteristics are provided. 2.1 power and ground lands the celeron d processor has 226 v cc (power), 24 v tt and 273 v ss (ground) inputs for on-chip power distribution. all power lands must be connected to v cc , while all vss lands must be connected to a system ground plane. the processor vcc lands must be supplied with the voltage determined by the v oltage id entification (vid) lands. twenty-four (24) signals are denoted as v tt that provide termination for the front side bus and power to the i/o buffers. a separate supply must be implemented for these lands that meets the v tt specifications outlined in ta b l e 4 . 2.2 decoupling guidelines due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. this may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. larger bulk storage (c bulk ), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. similarly, they act as a storage well for current when entering an idle condition from a running co ndition. the motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in ta b l e 4 . failure to do so can result in timing violations or reduced lifetime of the component. 2.2.1 v cc decoupling v cc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. this includes bulk capacitance with low effective series resistance (esr) to keep the voltage rail with in specifications during large swings in load current. in addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front si de bus and processor activity. consult the voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket for further information.
electrical specifications 14 datasheet 2.2.2 v tt decoupling decoupling must be provided on the motherboard. decoupling solutions must be sized to meet the expected load. to insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. a conservative decoupling solution would consist of a combin ation of low esr bulk capacitors and high frequency ceramic capacitors. 2.2.3 fsb decoupling the processor integrates signal termination on the die. in addition, some of the high frequency capacitance required for the fsb is included on the processor package. however, additional high frequency capacita nce must be added to the motherboard to properly decouple the return currents from the front side bus. bulk decoupling must also be provided by the motherboard for proper [a]gtl+ bus operation. 2.3 voltage identification the voltage identification (vid) specification for the processor is defined by the voltage regulator-down (vrd) 10.1 design guid e for desktop and transportable lga775 socket . the voltage set by the vid signals is the reference vr output voltage to be delivered to the processor vcc lands (see section 2.5.3 for v cc overshoot specifications). refer to ta b l e 1 4 for the dc specifications for these signals. a minimum voltage for each processor frequency is provided in ta b l e 4 . individual processor vid values may be calibrated during manufacturing such that two devices at the same core speed may have different default vid settings. this is reflected by the vid range values provided in ta b l e 4 . refer to the intel ? celeron ? d processor 300 sequence specification update for further details on specific valid core frequency and vid values of the processor. the processor uses 6 voltage identification signals, vid[5:0], to support automatic selection of power supply voltages. ta b l e 2 specifies the voltage level corresponding to the state of vid[5:0]. a ?1? in this table refers to a high voltage level and a ?0? refers to a low voltage level. if the processor sock et is empty (vid[5:0] = x11111), or the voltage regulation circuit cannot supply the vo ltage that is requested, it must disable itself. refer to the voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket for further details. the processor provides the ability to operate while transitioning to an adjacent vid and its associated processor core voltage (v cc ). this will represent a dc shift in the load line. note that a low-to-high or high-to-low voltage state change may result in as many vid transitions as necessary to reach the target core voltage. transitions above the specified vid are not permitted. ta b l e 4 includes vid step sizes and dc shift ranges. minimum and maximum voltages must be maintained as shown in ta b l e 5 and figure 1 as measured across the vcc_sense and vss_sense lands. the vrm or vrd used must be capable of regu lating its output to the value defined by the new vid. dc specifications for dynamic vid transitions are included in ta b l e 4 , and ta b l e 5 . refer to the voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket for further details.
datasheet 15 electrical specifications table 2. voltage identification definition vid5 vid4 vid3 vid2 vid1 vid0 vid vid5 vid4 vid3 vid2 vid1 vid0 vid 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875 1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000 0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125 1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250 0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375 1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500 0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625 1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750 0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875 1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000 0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125 1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250 0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375 1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500 0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625 1 1 1 1 1 1 vr output off 1 0 1 1 1 1 1.4750 0 1 1 1 1 1 vr output off 0 0 1 1 1 1 1.4875 1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000 0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125 1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250 0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375 1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500 0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625 1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750 0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875 1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.6000
electrical specifications 16 datasheet 2.4 reserved, unused, and testhi signals all reserved lands must re main unconnected. connection of these lands to v cc , v ss , v tt , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. see chapter 4 for a land listing of the processor and the location of all reserved lands. in a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. most unused gtl+ inputs should be left as no connects as gtl+ term ination is provided on the processor silicon. however, see ta b l e 7 for details on gtl+ signals that do not include on-die termination. unused active high inputs, should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected, ho wever this may interfere with some tap functions, complicate debug probing, and pr event boundary scan testing. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. resistor values should be within 20% of the im pedance of the motherboard trace for front side bus signals. for unused gtl+ input or i/o signals, use pull-up resistors of the same value as the on-die termination resistors (r tt ). for details see ta b l e 1 6 . tap, gtl+ asynchronous inputs, and gtl+ as ynchronous outputs do not include on-die termination. inputs and utilized outputs mu st be terminated on the motherboard. unused outputs may be terminated on the motherboard or left unconnected. note that leaving unused outputs unterminated may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. all testhi[13:0] lands should be individually connected to v tt via a pull-up resistor that matches the nominal trace impedance. the testhi signals may use individual pull-up resistors or be grouped together as detailed below. a matched resistor must be used for each group: ?testhi[1:0] ?testhi[7:2] ? testhi8 ? cannot be grouped with other testhi signals ? testhi9 ? cannot be grouped with other testhi signals ? testhi10 ? cannot be groupe d with other testhi signals ? testhi11 ? cannot be groupe d with other testhi signals ? testhi12 ? cannot be groupe d with other testhi signals ? testhi13 ? cannot be groupe d with other testhi signals however, use of boundary scan test will not be functional if these lands are connected together. for optimum noise margin, all pull-up resistor values used for testhi[13:0] lands should have a resistance value within 20% of the impedance of the board transmission line traces. for example, if the nominal trace impedance is 50 , then a value between 40 and 60 should be used.
datasheet 17 electrical specifications 2.5 voltage and current specification 2.5.1 absolute maximum and minimum ratings ta b l e 3 specifies absolute maximum and minimum ratings. within functional operation limits, functionality and long-term reliability can be expected. at conditions outside functional operatio n condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. if a device is returned to conditio ns within functional operation limits after having been subjected to conditions outs ide these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to condit ions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. table 3. absolute maximu m and minimum ratings symbol parameter min max unit notes 1, 2 notes: 1. for functional operation, all processor electr ical, signal quality, mechanical and thermal specifications must be satisfied. 2. excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. v cc core voltage with respect to v ss ?0.3 1.55 v - v tt fsb termination voltage with respect to v ss ?0.3 1.55 v - t c processor case temperature see chapter 5 see chapter 5 c - t storage processor storage temperature ?40 85 c 3, 4, 5 3. storage temperature is applicable to storage conditions only. in this scenario, the processor must not receive a clock, and no lands can be connecte d to a voltage bias. stor age within these limits will not affect the long-term reliability of the devi ce. for functional operatio n, please refer to the processor case temperature specifications. 4. this rating applies to the processor an d does not include any tray or packaging. 5. failure to adhere to this specification can affect the long term reliability of the processor.
electrical specifications 18 datasheet 2.5.2 dc voltage and current specification table 4. voltage and current specifications symbol parameter min typ max unit notes 1,2 notes: 1. unless otherwise noted, all specifications in this tabl e are based on estimates and si mulations or empirical data. these specifications will be updated with characterized data from silicon measurements at a later date. 2. adherence to the voltage specificatio ns for the processor are required to ensure reliable processor operation. vid range vid 1.25 ? 1.325 v 3 3. each processor is programmed with a maximum valid voltage identification value (vid) that is set at manufacturing and can not be altered. individual maximum vid values are calibrated during manufacturing such that two processors at the same frequency may ha ve different settings within the vid range. v cc processor number 356 352 v cc for 775_vr_config_05a 3.33 ghz 3.2 ghz refer to ta b l e 5 and figure 1 v 4, 5, 6 4. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. see section 2.3 and table 2 for more information. 5. the voltage specification requirements are measured across vcc_sense and vss_sense lands at the socket with a 100 mhz bandwidth oscilloscope, 1.5 pf maximum probe capacitance, and 1 m minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled into the oscilloscope probe. i cc processor number 356 352 v cc for 775_vr_config_05a 3.33 ghz 3.2 ghz ??100 a 7 processor number 360 i cc for 775_vr_config_06 3.46 ghz ?? 65 i sgnt processor number 356 352 i cc stop-grant for 775_vr_config_05a 3.33 ghz 3.2 ghz ?? 50 50 a 8,9 processor number 360 i cc stop-grant for 775_vr_config_06 3.46 ghz ?? tbd i tcc i cc tcc active ? ? i cc a 10 v tt fsb termination voltage (dc + ac specifications) 1.14 1.20 1.26 v 11, 12 vtt_out_left and vtt_out_right i cc dc current that may be drawn from vtt_out_left and vtt_out_right per land ??580ma i tt steady state fsb termination current ? ? 3.5 a 13, 14 i tt_power-up power-up fsb term ination current 4.5 a 13 , 15 i cc_vcca i cc for pll lands ?? 35ma i cc_vcciopll i cc for i/o pll land ?? 26ma i cc_gtlref i cc for gtlref ? ? 200 a
datasheet 19 electrical specifications 6. refer to table 5 and figure 1 for the minimum, typical, and maximum v cc allowed for a given current. the processor should not be subjected to any v cc and i cc combination wherein v cc exceeds v cc_max for a given current. 7. i cc_max is specified at v cc_max 8. the current specified is also for autohalt state. 9. i cc stop-grant is specified at v cc_max . 10.the maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the assertion of procho t#) is the same as the maximum i cc for the processor . 11.v tt must be provided via a separate volt age source and not be connected to v cc . this specification is measured at the land. 12.baseboard bandwidth is limited to 20 mhz. 13.this is maximum total current drawn from v tt plane by only the processor. th is specification does not include the current coming from r tt (through the signal line). refer to the voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket to determine the total i tt drawn by the system. 14.this is a steady-state i tt current specification that is applicable when both v tt and v cc are high. 15.this is a power-up peak current spec ification that is applicable when v tt is high and v cc is low.
electrical specifications 20 datasheet table 5. v cc static and transient tolera nce for 775_vr_config_05a and 775_vr_config_ 06 processors i cc (a) voltage deviation from vid setting (v) 1, 2, 3, 4 notes: 1. the loadline specification includes both static and transient limits except for overshoot allowed as shown in section 2.5.3 . 2. this table is intended to aid in reading discre te points on figure 1 . 3. the loadlines specify voltage limits at the die measured at the vcc_sense and vss_sense lands. voltage regulation feedba ck for voltage regula tor circuits must be taken from processor vcc and vss lands. refer to the voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket for socket loadline guidelines and vr implementation details. 4. adherence to this loadline specification for the celeron d processor is required to ensure reliable pr ocessor operation. maximum voltage 1.7 m typical voltage 1.75 m minimum voltage 1.8 m 0 0.000 -0.019 -0.038 5 -0.008 -0.027 -0.046 10 -0.016 -0.035 -0.055 15 -0.023 -0.043 -0.063 20 -0.031 -0.051 -0.071 25 -0.039 -0.059 -0.079 30 -0.047 -0.067 -0.088 35 -0.054 -0.075 -0.096 40 -0.062 -0.083 -0.104 45 -0.070 -0.091 -0.112 50 -0.078 -0.099 -0.121 55 -0.085 -0.107 -0.129 60 -0.093 -0.115 -0.137 65 -0.101 -0.123 -0.145 70 -0.109 -0.131 -0.154 75 -0.116 -0.139 -0.162 80 -0.121 -0.144 -0.167 85 -0.132 -0.155 -0.178 90 -0.140 -0.163 -0.187 95 -0.147 -0.171 -0.195 100 -0.155 -0.179 -0.203
datasheet 21 electrical specifications notes: 1. the loadline specification includes both static and transient limits except for overshoot allowed as shown in section 2.5.3 . 2. this loadline specification shows the deviation from the vid set point. 3. the loadlines specify voltage limits at the die measured at the vcc_sense and vss_sense lands. voltage regulation feedback for voltage regulator ci rcuits must be taken from processor vcc and vss lands. refer to the voltage regulator-down (vrd) 10.1 design guide for desktop an d transportable lga775 socket for socket loadline guidelines and vr implemen tation details. 2.5.3 v cc overshoot the celeron d processor can tolerate short transient overshoot events where v cc exceeds the vid voltage when transitioning fr om a high to low current load condition. this overshoot cannot exceed vid + v os_max (v os_max is the maximum allowable overshoot voltage). the time duration of the overshoot event must not exceed t os_max (t os_max is the maximum allowable time duration above vid). these specifications apply to the processor die voltage as measured across the vcc_sense and vss_sense lands. figure 1. v cc static and transient tolerance for 775_vr_config_05a and 775_vr_config_06 processors vid - 0.000 vid - 0.019 vid - 0.038 vid - 0.057 vid - 0.076 vid - 0.095 vid - 0.114 vid - 0.133 vid - 0.152 vid - 0.171 vid - 0.190 vid - 0.209 vid - 0.228 0 102030405060708090100 icc [a] vcc [v] vcc maximum vcc typical vcc minimum table 6. vcc overshoot specifications symbol parameter min max unit figure notes v os_max magnitude of v cc overshoot above vid ? 0.050 v 2 1 notes: 1. adherence to these specifications for the celero n d processor is required to ensure reliable processor operation. t os_max time duration of v cc overshoot above vid ? 25 s 2 1
electrical specifications 22 datasheet notes: 1. v os is measured overshoot voltage. 2. t os is measured time duration above vid. 2.5.4 die voltage validation overshoot events on processor mu st meet the specifications in ta b l e 6 when measured across the vcc_sense and vss_sense lands. overshoot events that are < 10 ns in duration may be ignored. these measuremen ts of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 mhz bandwidth limit. 2.6 signaling specifications most processor front side bus signals use gunning transceiver logic (gtl+) signaling technology. this technology provides im proved noise margins and reduced ringing through low voltage swings and controlled edge rates. platforms implement a termination voltage level for gtl+ signals defined as v tt . because platforms implement separate power planes for each processor (and chipset), separate v cc and v tt supplies are necessary. this configuration allows for improved noise tolerance as processor frequency increases. speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families. the gtl+ inputs require a reference voltage (g tlref) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. gtlref must be generated on the motherboard (see ta b l e 1 6 for gtlref specifications). termination resistors (r tt ) for gtl+ signals are provided on the processor silicon and are terminated to v tt . intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most gtl+ signals. figure 2. v cc overshoot example waveform time example overshoot waveform voltage (v) vid vid + 0.050 t os v os t os : overshoot time above vid v os : overshoot above vid
datasheet 23 electrical specifications 2.6.1 fsb signal groups the front side bus signals have been combined into groups by buffer type. gtl+ input signals have differential input buffers that us e gtlref[1:0] as a reference level. in this document, the term ?gtl+ input? refers to the gtl+ input group as well as the gtl+ i/o group when receiving. sim ilarly, ?gtl+ output? refers to the gtl+ output group as well as the gtl+ i/o group when driving. with the implementation of a source synchr onous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals that are dependent upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address) as well as the rising edge of bclk0. asychronous signals are still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. ta b l e 7 identifies which signals are common clock, source synchronous, and asynchronous. table 7. fsb signal groups (sheet 1 of 2) signal group type signals 1 gtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, rs[2:0]#, rsp#, trdy# gtl+ common clock i/o synchronous to bclk[1:0] ap[1:0]#, ads#, binit#, bnr#, bpm[5:0]#, br0#, dbsy#, dp[3:0]#, drdy#, hit#, hitm#, lock#, mcerr# gtl+ source synchronous i/o synchronous to assoc. strobe gtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# gtl+ asynchronous input a20m#, ignne#, init#, lint0/intr, lint1/nmi, smi#, stpclk#, pwrgood, reset# gtl+ asynchronous output ferr#/pbe#, ierr#, thermtrip# gtl+ asynchronous input/output prochot# tap input synchronous to tck tck, tdi, tms, trst# signals associated strobe req[4:0]#, a[16:3]# 2 adstb0# a[35:17]# 2 adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
electrical specifications 24 datasheet notes: 1. refer to section 4.2 for signal descriptions. 2. the value of these signals during the acti ve-to-inactive edge of reset# defines the processor configuration options. see section 6.1 for details. 3. in processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. . tap output synchronous to tck tdo fsb clock clock bclk[1:0], itp_clk[1:0] 3 power/other vcc, vtt, vcca, vcciopll, vid[5:0], vss, vssa, gtlref[1:0], comp[5:4,1:0], reserved, testhi[13:0], thermda, thermdc, vcc_sense, vcc_mb_regulation, vss_sense, vss_mb_regulation, bsel[2:0], sktocc#, dbr# 3 , vttpwrgd, bootselect, vtt_out_left, vtt_out_right, vtt_sel, ll _id[1:0], msid[1:0], fcx, impsel table 7. fsb signal groups (sheet 2 of 2) signal group type signals 1 table 8. signal characteristics signals with r tt signals with no r tt a[35:3]#, ads#, adst b[1:0]#, ap[1:0]#, binit#, bnr#, bootselect 1 , bpri#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, hit#, hi tm#, lock#, mcerr#, msid[1:0] 1 , prochot#, req[4:0]#, rs[2:0]#, rsp#, trdy#, impsel 2 notes: 1. these signals have a 500?5000 pull-up to v tt rather than on-die termination. a20m#, bclk[1:0], bpm[5:0]#, bsel[2:0], comp[5:4,1:0], ferr#/pbe#, ierr#, ignne#, init#, itp_cl k[1:0], lint0/intr, lint1/nmi, pwrgood, reset#, sktocc#, smi#, stpclk#, tdo, testhi[13:0], thermda, thermdc, thermtrip#, vid[5:0], vttpwrgd, gtlref[1:0], tck, tdi, tms, trst# open drain signals 2 2. signals that do not have r tt , nor are actively driven to their high-voltage level. thermtrip#, ferr#/pbe#, ierr#, bpm[5:0]#, br0#, tdo, vtt_sel, ll_id[1:0], fcx table 9. signal reference voltages gtlref v tt /2 bpm[5:0]#, lint0/intr, lint1/nmi, reset#, binit#, bnr#, hit#, hitm#, mcerr#, prochot#, br0#, a[35:0]#, ads#, ad stb[1:0]#, ap[1:0]#, bpri#, d[63:0]#, dbi[3: 0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, lock#, req[4:0]#, rs[2:0]#, rsp#, trdy# bootselect, vttpwrgd, a20m#, ignne#, init#, msid[1:0], pwrgood 1 , smi#, stpclk#, tck 1 , tdi 1 , tms 1 , trst# 1 notes: 1. these signals also have hysteresis added to the reference voltage. see table 12 for more information.
datasheet 25 electrical specifications 2.6.2 gtl+ asynchronous signals legacy input signals such as a20m#, ig nne#, init#, smi#, an d stpclk# use cmos input buffers. all of these si gnals follow the same dc requirements as gtl+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. these signals do not have setup or hold time specifications in relation to bclk[1:0]. all of the gtl+ asynchronous signals are re quired to be asserted/de-asserted for at least six bclks in order for the processor to recognize the proper signal state. see section 2.6.3 for the dc specifications for the gt l+ asynchronous signal groups. see section 6.2 for additional timing requirements for entering and leaving the low power states. 2.6.3 processor dc specifications the processor dc specifications in this section are defined at the processor core (pads) unless otherwise stated. all specifications apply to all frequencies and cache sizes unless otherwise stated. table 10. gtl+ signal group dc specifications symbol parameter min max unit notes 1 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. v il input low voltage 0.0 gtlref ? (0.10 * v tt )v 2, 3 2. v il is defined as the voltage range at a receiving agen t that will be interprete d as a logical low value. 3. the v tt referred to in these specific ations is the instantaneous v tt . v ih input high voltage gtlref + (0.10 * v tt )v tt v 4, 5, 3 4. v ih is defined as the voltage range at a receiving agen t that will be interpreted as a logical high value. 5. v ih and v oh may experience excursions above v tt . however, input signal drivers must comply with the signal quality specifications. v oh output high voltage 0.90*v tt v tt v 3 , 5 i ol output low current n/a v tt_max / [(0.50*r tt_min )+(r on_min )] a- i li input leakage current n/a 200 a 6 6. leakage to v ss with land held at v tt . i lo output leakage current n/a 200 a 7 7. leakage to v tt with land held at 300 mv. r on buffer on resistance 6 12
electrical specifications 26 datasheet . table 11. gtl+ asynchronous si gnal group dc specifications symbol parameter min max unit notes 1 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. v il input low voltage 0.0 v tt /2 ? (0.10 * v tt )v 2, 3 2. v il is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. lint0/intr and lint1/nmi use gtlref as a reference voltage. for these two signals v ih = gtlref + (0.10 * v tt ) and v il = gtlref ? (0.10 * v tt ). v ih input high voltage v tt /2 + (0.10 * v tt )v tt v 4, 5, 6, 3 4. v ih is defined as the vo ltage range at a receiving ag ent that will be interprete d as a logical high value. 5. v ih and v oh may experience excursions above v tt . however, input signal drivers must comply with the signal quality specifications. 6. the v tt referred to in these specificat ions refers to instantaneous v tt . v oh output high voltage 0.90*v tt v tt v 7, 5 , 6 7. all outputs are open drain. i ol output low current ? v tt / [(0.50*r tt_min )+(r on_min )] a 8 8. the maximum output current is based on maximum cu rrent handling capability of the buffer and is not specified into the test load. i li input leakage current n/a 200 a 9 9. leakage to v ss with land held at v tt . i lo output leakage current n/a 200 a 10 10.leakage to v tt with land held at 300 mv. r on buffer on resistance 6 12 table 12. pwrgood and tap sign al group dc specifications symbol parameter min max unit notes 1,2 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open drain. v hys input hysteresis 120 396 mv 3 3. v hys represents the amount of hysteresis, nominally centered about 0.5 * v tt , for all tap inputs. v t+ pwrgood input low- to-high threshold voltage 0.5 * (v tt + v hys_min + 0.24) 0.5 * (v tt + v hys_max + 0.24) v 4, 5 4. the v tt referred to in these specificat ions refers to instantaneous v tt . tap input low-to-high threshold voltage 0.5 * (v tt + v hys_min )0.5 * (v tt + v hys_max )v 4 v t- pwrgood input high- to-low threshold voltage 0.4 * v tt 0.6 * v tt v 4 tap input high-to-low threshold voltage 0.5 * (v tt ? v hys_max )0.5 * (v tt ? v hys_min )v 4 v oh output high voltage n/a v tt v 6, 4 i ol output low current ? 22.2 ma 7 i li input leakage current ? 200 a 8 i lo output leakage current ? 200a 9 r on buffer on resistance 6 12
datasheet 27 electrical specifications 5. 0.24 v is defined at 20% of nominal v tt of 1.2 v. 6. the tap signal group must meet the signal quality specifications. 7. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 8. leakage to v ss with land held at v tt . 9. leakage to v tt with land held at 300 mv. table 13. vttpwrgd dc specifications symbol parameter min typ max unit v il input low voltage ? ? 0.3 v v ih input high voltage 0.9 ? ? v table 14. bsel[2:0] and vi d[5:0] dc specifications symbol parameter max unit notes 1, 2 notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. these parameters are not tested an d are based on design simulations. r on (bsel) buffer on resistance 120 - r on (vid) buffer on resistance 120 - i ol max land current 2.4 ma - i lo output leakage current 200 a 3 3. leakage to v ss with land held at 1.2 v. v tol voltage tolerance v tt (max) v - table 15. bootselect dc specifications symbol parameter min typ max unit notes v il input low voltage ? ? 0.24 v 1 notes: 1. these parameters are not tested an d are based on design simulations. v ih input high voltage 0.96 ? ? v 1
electrical specifications 28 datasheet 2.6.3.1 gtl+ front side bus specifications in most cases, termination resistors are not required as these are integrated into the processor silicon. see ta b l e 8 for details on which gtl+ signals do not include on-die termination. valid high and low levels are determined by the input buffers by comparing with a reference voltage called gtlref. ta b l e 1 6 lists the gtlref specifications. the gtl+ reference voltage (gtlref) should be generated on the system board using high precision voltage divider circuits. table 16. gtl+ bus voltage definitions symbol parameter min typ max units notes 1 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. gtlref_pu gtlref pull up resistor 124 * 0.99 124 124 * 1.01 2 2. gtlref is to be generated from v tt by a voltage divider of 1% resi stors (one divider for each gtlref land). gtlref_pd gtlref pull down resistor 210 * 0.99 210 210 * 1.01 2 r pullup on die pull-up for bootselect signal 500 ? 5000 3 3. these pull-ups are to v tt . r tt 60 platform termination resistance 51 60 66 4 4. r tt is the on-die termination resistance measured at v tt /2 of the gtl+ output driver. the impsel land is used to select a 50 or 60 buffer and r tt value. 50 platform termination resistance 42 50 55 4 comp[1:0] 60 platform termination comp resistance 59.8 60.4 61 5 5. comp resistance must be provided on the system board with 1% resistors. see the applicable platform design guide for implementation details. comp[1:0] resistors are to v ss . comp[5:4] resistors are to v tt . 50 platform termination comp resistance 49.9 * 0.99 49.9 49.9 * 1.01 5 comp[5:4] 60 platform termination comp resistance 59.8 60.4 61 5 50 platform termination comp resistance 49.9 * 0.99 49.9 49.9 * 1.01 5
datasheet 29 electrical specifications 2.7 clock specifications 2.7.1 front side bus clock (bcl k[1:0]) and proc essor clocking bclk[1:0] directly controls the fsb interface speed as well as the core frequency of the processor. as in previous generation processors, the celeron d processor core frequency is a multiple of the bclk[1:0] fr equency. the processor bus ratio multiplier will be set at its default ratio during manufacturing. refer to ta b l e 1 7 for the celeron d processor supported ratios. the celeron d processor uses a differential clocking implementation. for more information on the celeron d processor clocking, contact your intel field representative. 2.7.2 fsb frequency select signals (bsel[2:0]) the bsel[2:0] signals are used to select the frequency of the processor input clock (bclk[1:0]). ta b l e 1 8 defines the possible combinations of the signals and the frequency associated with each combination. the required frequency is determined by the processor, chipset, and clock synthesizer. all agents must operate at the same frequency. the celeron d processor will operate at an 533 mhz fsb frequency (selected by a 133 mhz bclk[1:0] frequency). for more information about these signals, refer to section 4.2 . table 17. core frequency to fs b multiplier configuration multiplication of system core frequency to fsb frequency core frequency (133 mhz bclk/ 533 mhz fsb) notes 1, 2 notes: 1. individual processors operate only at or below the rated frequency. 2. listed frequencies are not necessarily committed production frequencies. 1/12 1.6 ghz - 1/13 1.8 ghz - 1/14 1.9 ghz - 1/15 2 ghz - 1/16 2.1 ghz - 1/17 2.3 ghz - 1/18 2.4 ghz - 1/19 2.5 ghz - 1/20 2.7 ghz - 1/21 2.8 ghz - 1/22 2.9 ghz - 1/23 3 ghz - 1/24 3.2 ghz - 1/25 3.3 ghz -
electrical specifications 30 datasheet 2.7.3 phase lock lo op (pll) and filter v cca and v cciopll are power sources required by the pll clock generators for the celeron d processor silicon. since these plls are analog in nature, they require low noise power supplies for minimum jitter. jitter is detrimental to the system: it degrades external i/o timings as well as internal co re timings (i.e., maximum frequency). to prevent this degradation, these supplies must be low pass filtered from v tt . the ac low-pass requirements, with input at v tt are as follows: ? < 0.2 db gain in pass band ? < 0.5 db attenuation in pass band < 1 hz ? > 34 db attenuation from 1 mhz to 66 mhz ? > 28 db attenuation from 66 mhz to core frequency the filter requirements are illustrated in figure 3 . table 18. bsel[2:0] frequency table for bclk[1:0] bsel2 bsel1 bsel0 fsb frequency ll lreserved l l h 133 mhz lh hreserved lh lreserved hh lreserved hh hreserved hl hreserved hl lreserved
datasheet 31 electrical specifications . notes: 1. diagram not to scale. 2. no specification for frequencie s beyond fcore (core frequency). 3. f peak , if existent, should be less than 0.05 mhz. 4. f core represents the maximum core frequ ency supported by the platform. figure 3. phase lock loop (pll) filter requirements 0 db ?28 db ?34 db 0.2 db ?0.5 db 1 mhz 66 mhz fcore fpeak 1 hz dc passband high frequency band filt s forbidden zone forbidden zone
electrical specifications 32 datasheet 2.7.4 bclk[1:0] specifications table 19. front side bus diffe rential bclk specifications symbol parameter min typ max unit notes 1 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. v l input low voltage -0.150 0.00 0 n/a v - v h input high voltage 0.660 0.70 0 0.850 v - v cross(abs) absolute crossing point 0.250 n/a 0.550 v 2 , 3 2. crossing voltage is defined as the instantaneous voltage value when the rising edge of bclk0 equals the falling edge of bclk1. 3. the crossing point must meet the absolute and relative crossing point specifications simultaneously. v cross(rel) relative crossing point 0.250 + 0.5( v h avg ? 0.700) n/a 0.550 + 0.5( v h avg ? 0.700) v 4, 3 , 5 4. v havg is the statistical average of the v h measured by the oscilloscope. 5. v havg can be measured directly using ?vtop? on ag ilent* oscilloscopes and ?high? on tektronix* oscilloscopes. v cross range of crossing points n/a n/a 0.140 v - v os overshoot n/a n/a v h + 0.3 v 6 6. overshoot is defined as the absolu te value of the maximum voltage. v us undershoot -0.300 n/a n/a v 7 7. undershoot is defined as the absolute value of the minimum voltage. v rbm ringback margin 0.200 n/a n/a v 8 8. ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum falling edge ringback. v tm threshold region v cross ? 0.100 n/a v cross + 0.100 v 9 9. threshold region is defined as a region entered around the crossing point voltage in which the differential receiver swit ches. it includes input threshold hysteresis.
datasheet 33 package mechanical specifications 3 package mechanical specifications the celeron d processor is packaged in a f lip-chip land grid array (fc-lga4) package that interfaces with the motherboard via an lga775 socket. the package consists of a processor core mounted on a substrate land-carrier. an integrated heat spreader (ihs) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. figure 4 shows a sketch of the processor package components and how th ey are assembled together. refer to the lga775 socket mechanical design guide for complete details on the lga775 socket. the package components shown in figure 4 include the following: ? integrated heat spreader (ihs) ? thermal interface material (tim) ? processor core (die) ? package substrate ? capacitors note: 1. socket and motherboard are included for refe rence and are not part of processor package. 3.1 package mechanical drawing the package mechanical drawings are shown in figure 5 and figure 6 . the drawings include dimensions necessary to design a thermal solution for the processor. these dimensions include: ? package reference with tolerances (total height, length, width, etc.) ? ihs parallelism and tilt ? land dimensions ? top-side and back-side component keep-out dimensions ? reference datums ? all drawing dimensions are in mm [in]. ? guidelines on potential ihs flatness variation with socket load plate actuation and installation of the cooling solution is av ailable in the processor thermal/mechanical design guidelines. figure 4. processor package assembly sketch system board lga775 socket capacitors tim core (die) ihs substrate
package mechanical specifications 34 datasheet figure 5. processor package drawing (sheet 1 of 3)
datasheet 35 package mechanical specifications figure 6. processor package drawing sheet 2 of 3
package mechanical specifications 36 datasheet figure 7. processor package drawing sheet 3 of 3
datasheet 37 package mechanical specifications 3.2 processor component keep-out zones the processor may contain components on the substrate that define component keep- out zone requirements. a thermal and mechanical solution design must not intrude into the required keep-out zones. decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. see figure 5 and figure 6 for keep-out zones. the location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in. 3.3 package loading specifications ta b l e 2 0 provides dynamic and static load specifications for the processor package. these mechanical maximum load limits shou ld not be exceeded during heatsink assembly, shipping conditions, or standard use condition. also, any mechanical system or component testing should not exceed the maximum limits. the processor package substrate should not be used as a mechanic al reference or load -bearing surface for thermal and mechanical solution. the mi nimum loading specification must be maintained by any thermal and mechanical solutions. . 3.4 package handling guidelines ta b l e 2 1 includes a list of guidelines on pa ckage handling in terms of recommended maximum loading on the processor ihs relati ve to a fixed substrate. these package handling loads may be experien ced during heatsink removal. table 20. processor lo ading specifications parameter minimum maximum notes static 80 n [17 lbf] 311 n [70 lbf] 1, 2, 3 notes: 1. these specifications apply to uniform compressive loading in a direction normal to the processor ihs. 2. this is the maximum force that can be applied by a heatsink retention clip. the clip must also provide the minimum specified lo ad on the processor package. 3. these specifications are based on limited testin g for design characterizat ion. loading limits are for the package only and do not include the limits of the processor socket. dynamic ? 756 n [170 lbf] 1 , 3 , 4 4. dynamic loading is defi ned as an 11 ms duration average lo ad superimposed on the static load requirement. table 21. package handling guidelines parameter maximum recommended notes shear 311 n [70 lbf] 1, 2 notes: 1. a shear load is defined as a load applied to the ihs in a directio n parallel to the ihs top surface. 2. these guidelines are based on limite d testing for design characterization. tensile 111 n [25 lbf] 2 , 3 3. a tensile load is defined as a pulling load appl ied to the ihs in a direction normal to the ihs surface. torque 3.95 n-m [35 lbf-in] 2 , 4 4. a torque load is defined as a twisting load applied to the ihs in an axis of rotation normal to the ihs top surface.
package mechanical specifications 38 datasheet 3.5 package insertion specifications the celeron d processor can be inserted into and removed from a lga775 socket 15 times. the socket should meet the lga775 requirements detailed in the lga775 socket mechanical design guide . 3.6 processor mass specification the typical mass of the celeron d processor is 21.5 g [0.76 oz]. this mass [weight] includes all the components that are included in the package. 3.7 processor materials ta b l e 2 2 lists some of the package components and associated materials. 3.8 processor markings figure 8 shows the topside markings on the proc essor. this diagram is to aid in the identification of the celeron d processor. table 22. processor materials component material integrated heat spreader (ihs) nickel plated copper substrate fiber reinforced resin substrate lands gold plated copper figure 8. processor top-side marking example atpo s/n processor number/ s-spec/ country of assy intel xxxxxxxx 3.33ghz/512k/533/05a 356 slxxx [coo] [fpo] m ? ?0 5 frequency/l2 cache/bus/fmb fpo 2-d matrix mark unique unit identifier atpo serial # brand
datasheet 39 package mechanical specifications 3.9 processor land coordinates figure 9 shows the top view of the processor land coordinates. the coordinates are referred to throughout the docume nt to identify processor lands. . figure 9. processor la nd coordinates and quadrants (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 socket 775 quadrants top view v cc / v ss v tt / clocks data address/ common clock/ async
package mechanical specifications 40 datasheet
datasheet 41 land listing and signal descriptions 4 land listing and signal descriptions this chapter provides the processor la nd assignment and signal descriptions. 4.1 processor land assignments this section contains the land listings for th e processor. the land-out footprint is shown in figure 10 and figure 11 . these figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). ta b l e 2 3 is a listing of all processor lands ordered alphabetically by land (signal) name. ta b l e 2 4 is also a listing of all processor lands; the ordering is by land number.
land listing and signal descriptions 42 datasheet figure 10.land-out diagram (top view ? left side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 an vcc vcc vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc am vcc vcc vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc al vcc vcc vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc ak vss vss vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc aj vss vss vss vss vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc ah vcc vcc vcc vcc vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc ag vcc vcc vcc vcc vcc vcc vss vss vcc vcc vss vcc vcc vss vss vcc af vss vss vss vss vss vss vss vss vcc vcc vss vcc vcc vss vss vcc ae vss vss vss vss vss vss vss vcc vcc vcc vss vcc vcc vss vss vcc ad vcc vcc vcc vcc vcc vcc vcc vcc ac vcc vcc vcc vcc vcc vcc vcc vcc ab vss vss vss vss vss vss vss vss aa vss vss vss vss vss vss vss vss y vcc vcc vcc vcc vcc vcc vcc vcc w vcc vcc vcc vcc vcc vcc vcc vcc v vss vss vss vss vss vss vss vss u vcc vcc vcc vcc vcc vcc vcc vcc t vcc vcc vcc vcc vcc vcc vcc vcc r vss vss vss vss vss vss vss vss p vss vss vss vss vss vss vss vss n vcc vcc vcc vcc vcc vcc vcc vcc m vcc vcc vcc vcc vcc vcc vcc vcc l vss vss vss vss vss vss vss vss k vcc vcc vcc vcc vcc vcc vcc vcc j vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc dp3# dp0# vcc h bsel1 fc15 vss vss vss vss vss vss vss vss vss vss vss vss dp2# dp1# g bsel2 bsel0 bclk1 testhi4 testhi5 testhi3 testhi6 reset# d47# d44# dstbn2# dstbp2# d35# d36# d32# d31# f rsvd bclk0 vtt_sel testhi0 testhi2 testhi7 rsvd vss d43# d41# vss d38# d37# vss d30# e vss vss vss vss vss fc17 rsvd d45# d42# vss d40# d39# vss d34# d33# d vtt vtt vtt vtt vtt vtt vss rsvd d46# vss d48# dbi2# vss d49# rsvd vss c vtt vtt vtt vtt vtt vtt vss vccio pll vss d58# dbi3# vss d54# dstbp3# vss d51# b vtt vtt vtt vtt vtt vtt vss vssa d63# d59# vss d60# d57# vss d55# d53# a vtt vtt vtt vtt vtt vtt vss vcca d62# vss rsvd d61# vss d56# dstbn3# vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
datasheet 43 land listing and signal descriptions figure 11.land-out diagram (top view ? right side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vcc vss vcc vcc vss vcc vcc fc16 vss_mb_ regulation vcc_mb_ regulation vss_ sense vcc_ sense vss vss an vcc vss vcc vcc vss vcc vcc fc12 vttpwrgd fc11 vss vid2 vid0 vss am vcc vss vcc vcc vss vcc vcc vss vid3 vid1 vid5 vss prochot# thermda al vcc vss vcc vcc vss vcc vcc vss fc8 vss vid4 itp_clk0 vss thermdc ak vcc vss vcc vcc vss vcc vcc vss a35# a34# vss itp_clk1 bpm0# bpm1# aj vcc vss vcc vcc vss vcc vcc vss vss a33# a32# vss rsvd vss ah vcc vss vcc vcc vss vcc vcc vss a29# a31# a30# bpm5# bpm3# trst# ag vcc vss vcc vcc vss vcc vcc vss vss a27# a28# vss bpm4# tdo af vcc vss vcc vcc vss vcc sktocc# vss rsvd vss rsvd rsvd vss tck ae vcc vss a22# adstb1# vss binit# bpm2# tdi ad vcc vss vss a25# rsvd vss dbr# tms ac vcc vss a17# a24# a26# mcerr# ierr# vss ab vcc vss vss a23# a21# vss ll_id1 vtt_out_ right aa vcc vss a19# vss a20# rsvd vss boot select y vcc vss a18# a16# vss testhi1 testhi12 msid0 w vcc vss vss a14# a15# vss ll_id0 msid1 v vcc vss a10# a12# a13# ap1# ap0# vss u vcc vss vss a9# a11# vss comp5 comp1 t vcc vss adstb0# vss a8# ferr#/ pbe# vss fc2 r vcc vss a4# rsvd vss init# smi# testhi11 p vcc vss vss rsvd rsvd vss ignne# pwrgood n vcc vss req2# a5# a7# stpclk# thermtri p# vss m vcc vss vss a3# a6# vss testhi13 lint1 l vcc vss req3# vss req0# a20m# vss lint0 k vcc vcc vcc vcc vcc vcc vcc vss req4# req1# vss rsvd comp4 vtt_out_ left j vss vss vss vss vss vss vss vss vss testhi10 rsp# vss gtlref1 gtlref0 h d29# d27# dstbn1# dbi1# rsvd d16# bpri# defer# rsvd fc7 testhi9 testhi8 fc1 vss g d28# vss d24# d23# vss d18# d17# vss impsel rs1# vss br0# fc5 f vss d26# dstbp1# vss d21# d19# vss rsvd rsvd rsvd hitm# trdy# vss e rsvd d25# vss d15# d22# vss d12# d20# vss vss hit# vss ads# rsvd d d52# vss d14# d11# vss rsvd dstbn0# vss d3# d1# vss lock# bnr# drdy# c vss rsvd d13# vss d10# dstbp0# vss d6# d5# vss d0# rs0# dbsy# vss b d50# comp0 vss d9# d8# vss dbi0# d7# vss d4# d2# rs2# vss a 14 13 12 11 10 9 8 7 6 5 4 3 2 1
land listing and signal descriptions 44 datasheet table 23.alphabetical land assignments land name land # signal buffer type direction a3# l5 source synch input/output a4# p6 source synch input/output a5# m5 source synch input/output a6# l4 source synch input/output a7# m4 source synch input/output a8# r4 source synch input/output a9# t5 source synch input/output a10# u6 source synch input/output a11# t4 source synch input/output a12# u5 source synch input/output a13# u4 source synch input/output a14# v5 source synch input/output a15# v4 source synch input/output a16# w5 source synch input/output a17# ab6 source synch input/output a18# w6 source synch input/output a19# y6 source synch input/output a20# y4 source synch input/output a20m# k3 asynch gtl+ input a21# aa4 source synch input/output a22# ad6 source synch input/output a23# aa5 source synch input/output a24# ab5 source synch input/output a25# ac5 source synch input/output a26# ab4 source synch input/output a27# af5 source synch input/output a28# af4 source synch input/output a29# ag6 source synch input/output a30# ag4 source synch input/output a31# ag5 source synch input/output a32# ah4 source synch input/output a33# ah5 source synch input/output a34# aj5 source synch input/output a35# aj6 source synch input/output ads# d2 common clock input/output adstb0# r6 source synch input/output adstb1# ad5 source synch input/output ap0# u2 common clock input/output ap1# u3 common clock input/output bclk0 f28 clock input bclk1 g28 clock input binit# ad3 common clock input/output bnr# c2 common clock input/output bootselect y1 power/other input bpm0# aj2 common clock input/output bpm1# aj1 common clock input/output bpm2# ad2 common clock input/output bpm3# ag2 common clock input/output bpm4# af2 common clock input/output bpm5# ag3 common clock input/output bpri# g8 common clock input br0# f3 common clock input/output bsel0 g29 power/other output bsel1 h30 power/other output bsel2 g30 power/other output comp0 a13 power/other input comp1 t1 power/other input comp4 j2 power/other input comp5 t2 power/other input d0# b4 source synch input/output d1# c5 source synch input/output d2# a4 source synch input/output d3# c6 source synch input/output d4# a5 source synch input/output d5# b6 source synch input/output d6# b7 source synch input/output d7# a7 source synch input/output d8# a10 source synch input/output d9# a11 source synch input/output d10# b10 source synch input/output d11# c11 source synch input/output d12# d8 source synch input/output d13# b12 source synch input/output d14# c12 source synch input/output d15# d11 source synch input/output d16# g9 source synch input/output d17# f8 source synch input/output d18# f9 source synch input/output table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions datasheet 45 d19# e9 source synch input/output d20# d7 source synch input/output d21# e10 source synch input/output d22# d10 source synch input/output d23# f11 source synch input/output d24# f12 source synch input/output d25# d13 source synch input/output d26# e13 source synch input/output d27# g13 source synch input/output d28# f14 source synch input/output d29# g14 source synch input/output d30# f15 source synch input/output d31# g15 source synch input/output d32# g16 source synch input/output d33# e15 source synch input/output d34# e16 source synch input/output d35# g18 source synch input/output d36# g17 source synch input/output d37# f17 source synch input/output d38# f18 source synch input/output d39# e18 source synch input/output d40# e19 source synch input/output d41# f20 source synch input/output d42# e21 source synch input/output d43# f21 source synch input/output d44# g21 source synch input/output d45# e22 source synch input/output d46# d22 source synch input/output d47# g22 source synch input/output d48# d20 source synch input/output d49# d17 source synch input/output d50# a14 source synch input/output d51# c15 source synch input/output d52# c14 source synch input/output d53# b15 source synch input/output d54# c18 source synch input/output d55# b16 source synch input/output d56# a17 source synch input/output d57# b18 source synch input/output table 23.alphabetical land assignments land name land # signal buffer type direction d58# c21 source synch input/output d59# b21 source synch input/output d60# b19 source synch input/output d61# a19 source synch input/output d62# a22 source synch input/output d63# b22 source synch input/output dbi0# a8 source synch input/output dbi1# g11 source synch input/output dbi2# d19 source synch input/output dbi3# c20 source synch input/output dbr# ac2 power/other output dbsy# b2 common clock input/output defer# g7 common clock input dp0# j16 common clock input/output dp1# h15 common clock input/output dp2# h16 common clock input/output dp3# j17 common clock input/output drdy# c1 common clock input/output dstbn0# c8 source synch input/output dstbn1# g12 source synch input/output dstbn2# g20 source synch input/output dstbn3# a16 source synch input/output dstbp0# b9 source synch input/output dstbp1# e12 source synch input/output dstbp2# g19 source synch input/output dstbp3# c17 source synch input/output fc1 g2 power/other input fc2 r1 power/other input fc5 f2 common clock input fc7 g5 source synch output fc8 ak6 fc11 am5 power/other output fc12 am7 power/other output fc15 h29 power/other output fc16 an7 power/other output fc17 e24 power/other output ferr#/pbe# r3 asynch gtl+ output gtlref0 h1 power/other input gtlref1 h2 power/other input table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions 46 datasheet hit# d4 common clock input/output hitm# e4 common clock input/output ierr# ab2 asynch gtl+ output ignne# n2 asynch gtl+ input impsel f6 power/other input init# p3 asynch gtl+ input itp_clk0 ak3 tap input itp_clk1 aj3 tap input lint0 k1 asynch gtl+ input lint1 l1 asynch gtl+ input ll_id0 v2 power/other output ll_id1 aa2 power/other output lock# c3 common clock input/output mcerr# ab3 common clock input/output msid0 w1 power/other output msid1 v1 power/other output prochot# al2 asynch gtl+ input/output pwrgood n1 power/other input req0# k4 source synch input/output req1# j5 source synch input/output req2# m6 source synch input/output req3# k6 source synch input/output req4# j6 source synch input/output reserved b13 reserved a20 reserved ac4 reserved ae3 reserved ae4 reserved ae6 reserved ah2 reserved c9 reserved d1 reserved d14 reserved d16 reserved d23 reserved e23 reserved e5 reserved e6 reserved e7 table 23.alphabetical land assignments land name land # signal buffer type direction reserved f23 reserved f29 reserved g10 reserved g6 reserved j3 reserved n4 reserved n5 reserved p5 reserved y3 reset# g23 common clock input rs0# b3 common clock input rs1# f5 common clock input rs2# a3 common clock input rsp# h4 common clock input sktocc# ae8 power/other output smi# p2 asynch gtl+ input stpclk# m3 asynch gtl+ input tck ae1 tap input tdi ad1 tap input tdo af1 tap output testhi0 f26 power/other input testhi1 w3 power/other input testhi2 f25 power/other input testhi3 g25 power/other input testhi4 g27 power/other input testhi5 g26 power/other input testhi6 g24 power/other input testhi7 f24 power/other input testhi8 g3 power/other input testhi9 g4 power/other input testhi10 h5 power/other input testhi11 p1 power/other input testhi12 w2 power/other input testhi13 l2 asynch gtl+ input thermda al1 power/other thermdc ak1 power/other thermtrip# m2 asynch gtl+ output tms ac1 tap input trdy# e3 common clock input table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions datasheet 47 trst# ag1 tap input vcc aa8 power/other vcc ab8 power/other vcc ac23 power/other vcc ac24 power/other vcc ac25 power/other vcc ac26 power/other vcc ac27 power/other vcc ac28 power/other vcc ac29 power/other vcc ac30 power/other vcc ac8 power/other vcc ad23 power/other vcc ad24 power/other vcc ad25 power/other vcc ad26 power/other vcc ad27 power/other vcc ad28 power/other vcc ad29 power/other vcc ad30 power/other vcc ad8 power/other vcc ae11 power/other vcc ae12 power/other vcc ae14 power/other vcc ae15 power/other vcc ae18 power/other vcc ae19 power/other vcc ae21 power/other vcc ae22 power/other vcc ae23 power/other vcc ae9 power/other vcc af11 power/other vcc af12 power/other vcc af14 power/other vcc af15 power/other vcc af18 power/other vcc af19 power/other vcc af21 power/other vcc af22 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vcc af8 power/other vcc af9 power/other vcc ag11 power/other vcc ag12 power/other vcc ag14 power/other vcc ag15 power/other vcc ag18 power/other vcc ag19 power/other vcc ag21 power/other vcc ag22 power/other vcc ag25 power/other vcc ag26 power/other vcc ag27 power/other vcc ag28 power/other vcc ag29 power/other vcc ag30 power/other vcc ag8 power/other vcc ag9 power/other vcc ah11 power/other vcc ah12 power/other vcc ah14 power/other vcc ah15 power/other vcc ah18 power/other vcc ah19 power/other vcc ah21 power/other vcc ah22 power/other vcc ah25 power/other vcc ah26 power/other vcc ah27 power/other vcc ah28 power/other vcc ah29 power/other vcc ah30 power/other vcc ah8 power/other vcc ah9 power/other vcc aj11 power/other vcc aj12 power/other vcc aj14 power/other vcc aj15 power/other vcc aj18 power/other table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions 48 datasheet vcc aj19 power/other vcc aj21 power/other vcc aj22 power/other vcc aj25 power/other vcc aj26 power/other vcc aj8 power/other vcc aj9 power/other vcc ak11 power/other vcc ak12 power/other vcc ak14 power/other vcc ak15 power/other vcc ak18 power/other vcc ak19 power/other vcc ak21 power/other vcc ak22 power/other vcc ak25 power/other vcc ak26 power/other vcc ak8 power/other vcc ak9 power/other vcc al11 power/other vcc al12 power/other vcc al14 power/other vcc al15 power/other vcc al18 power/other vcc al19 power/other vcc al21 power/other vcc al22 power/other vcc al25 power/other vcc al26 power/other vcc al29 power/other vcc al30 power/other vcc al8 power/other vcc al9 power/other vcc am11 power/other vcc am12 power/other vcc am14 power/other vcc am15 power/other vcc am18 power/other vcc am19 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vcc am21 power/other vcc am22 power/other vcc am25 power/other vcc am26 power/other vcc am29 power/other vcc am30 power/other vcc am8 power/other vcc am9 power/other vcc an11 power/other vcc an12 power/other vcc an14 power/other vcc an15 power/other vcc an18 power/other vcc an19 power/other vcc an21 power/other vcc an22 power/other vcc an25 power/other vcc an26 power/other vcc an29 power/other vcc an30 power/other vcc an8 power/other vcc an9 power/other vcc j10 power/other vcc j11 power/other vcc j12 power/other vcc j13 power/other vcc j14 power/other vcc j15 power/other vcc j18 power/other vcc j19 power/other vcc j20 power/other vcc j21 power/other vcc j22 power/other vcc j23 power/other vcc j24 power/other vcc j25 power/other vcc j26 power/other vcc j27 power/other vcc j28 power/other table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions datasheet 49 vcc j29 power/other vcc j30 power/other vcc j8 power/other vcc j9 power/other vcc k23 power/other vcc k24 power/other vcc k25 power/other vcc k26 power/other vcc k27 power/other vcc k28 power/other vcc k29 power/other vcc k30 power/other vcc k8 power/other vcc l8 power/other vcc m23 power/other vcc m24 power/other vcc m25 power/other vcc m26 power/other vcc m27 power/other vcc m28 power/other vcc m29 power/other vcc m30 power/other vcc m8 power/other vcc n23 power/other vcc n24 power/other vcc n25 power/other vcc n26 power/other vcc n27 power/other vcc n28 power/other vcc n29 power/other vcc n30 power/other vcc n8 power/other vcc p8 power/other vcc r8 power/other vcc t23 power/other vcc t24 power/other vcc t25 power/other vcc t26 power/other vcc t27 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vcc t28 power/other vcc t29 power/other vcc t30 power/other vcc t8 power/other vcc u23 power/other vcc u24 power/other vcc u25 power/other vcc u26 power/other vcc u27 power/other vcc u28 power/other vcc u29 power/other vcc u30 power/other vcc u8 power/other vcc v8 power/other vcc w23 power/other vcc w24 power/other vcc w25 power/other vcc w26 power/other vcc w27 power/other vcc w28 power/other vcc w29 power/other vcc w30 power/other vcc w8 power/other vcc y23 power/other vcc y24 power/other vcc y25 power/other vcc y26 power/other vcc y27 power/other vcc y28 power/other vcc y29 power/other vcc y30 power/other vcc y8 power/other vcc_mb_ regulation an5 power/other output vcc_sense an3 power/other output vcca a23 power/other vcciopll c23 power/other vid0 am2 power/other output vid1 al5 power/other output vid2 am3 power/other output table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions 50 datasheet vid3 al6 power/other output vid4 ak4 power/other output vid5 al4 power/other output vss b1 power/other vss b11 power/other vss b14 power/other vss b17 power/other vss b20 power/other vss b24 power/other vss b5 power/other vss b8 power/other vss a12 power/other vss a15 power/other vss a18 power/other vss a2 power/other vss a21 power/other vss a24 power/other vss a6 power/other vss a9 power/other vss aa23 power/other vss aa24 power/other vss aa25 power/other vss aa26 power/other vss aa27 power/other vss aa28 power/other vss aa29 power/other vss aa3 power/other vss aa30 power/other vss aa6 power/other vss aa7 power/other vss ab1 power/other vss ab23 power/other vss ab24 power/other vss ab25 power/other vss ab26 power/other vss ab27 power/other vss ab28 power/other vss ab29 power/other vss ab30 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vss ab7 power/other vss ac3 power/other vss ac6 power/other vss ac7 power/other vss ad4 power/other vss ad7 power/other vss ae10 power/other vss ae13 power/other vss ae16 power/other vss ae17 power/other vss ae2 power/other vss ae20 power/other vss ae24 power/other vss ae25 power/other vss ae26 power/other vss ae27 power/other vss ae28 power/other vss ae29 power/other vss ae30 power/other vss ae5 power/other vss ae7 power/other vss af10 power/other vss af13 power/other vss af16 power/other vss af17 power/other vss af20 power/other vss af23 power/other vss af24 power/other vss af25 power/other vss af26 power/other vss af27 power/other vss af28 power/other vss af29 power/other vss af3 power/other vss af30 power/other vss af6 power/other vss af7 power/other vss ag10 power/other vss ag13 power/other table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions datasheet 51 vss ag16 power/other vss ag17 power/other vss ag20 power/other vss ag23 power/other vss ag24 power/other vss ag7 power/other vss ah1 power/other vss ah10 power/other vss ah13 power/other vss ah16 power/other vss ah17 power/other vss ah20 power/other vss ah23 power/other vss ah24 power/other vss ah3 power/other vss ah6 power/other vss ah7 power/other vss aj10 power/other vss aj13 power/other vss aj16 power/other vss aj17 power/other vss aj20 power/other vss aj23 power/other vss aj24 power/other vss aj27 power/other vss aj28 power/other vss aj29 power/other vss aj30 power/other vss aj4 power/other vss aj7 power/other vss ak10 power/other vss ak13 power/other vss ak16 power/other vss ak17 power/other vss ak2 power/other vss ak20 power/other vss ak23 power/other vss ak24 power/other vss ak27 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vss ak28 power/other vss ak29 power/other vss ak30 power/other vss ak5 power/other vss ak7 power/other vss al10 power/other vss al13 power/other vss al16 power/other vss al17 power/other vss al20 power/other vss al23 power/other vss al24 power/other vss al27 power/other vss al28 power/other vss al3 power/other vss al7 power/other vss am1 power/other vss am10 power/other vss am13 power/other vss am16 power/other vss am17 power/other vss am20 power/other vss am23 power/other vss am24 power/other vss am27 power/other vss am28 power/other vss am4 power/other vss an1 power/other vss an10 power/other vss an13 power/other vss an16 power/other vss an17 power/other vss an2 power/other vss an20 power/other vss an23 power/other vss an24 power/other vss an27 power/other vss an28 power/other vss c10 power/other table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions 52 datasheet vss c13 power/other vss c16 power/other vss c19 power/other vss c22 power/other vss c24 power/other vss c4 power/other vss c7 power/other vss d12 power/other vss d15 power/other vss d18 power/other vss d21 power/other vss d24 power/other vss d3 power/other vss d5 power/other vss d6 power/other vss d9 power/other vss e11 power/other vss e14 power/other vss e17 power/other vss e2 power/other vss e20 power/other vss e25 power/other vss e26 power/other vss e27 power/other vss e28 power/other vss e29 power/other vss e8 power/other vss f10 power/other vss f13 power/other vss f16 power/other vss f19 power/other vss f22 power/other vss f4 power/other vss f7 power/other vss g1 power/other vss h10 power/other vss h11 power/other vss h12 power/other vss h13 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vss h14 power/other vss h17 power/other vss h18 power/other vss h19 power/other vss h20 power/other vss h21 power/other vss h22 power/other vss h23 power/other vss h24 power/other vss h25 power/other vss h26 power/other vss h27 power/other vss h28 power/other vss h3 power/other vss h6 power/other vss h7 power/other vss h8 power/other vss h9 power/other vss j4 power/other vss j7 power/other vss k2 power/other vss k5 power/other vss k7 power/other vss l23 power/other vss l24 power/other vss l25 power/other vss l26 power/other vss l27 power/other vss l28 power/other vss l29 power/other vss l3 power/other vss l30 power/other vss l6 power/other vss l7 power/other vss m1 power/other vss m7 power/other vss n3 power/other vss n6 power/other vss n7 power/other table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions datasheet 53 vss p23 power/other vss p24 power/other vss p25 power/other vss p26 power/other vss p27 power/other vss p28 power/other vss p29 power/other vss p30 power/other vss p4 power/other vss p7 power/other vss r2 power/other vss r23 power/other vss r24 power/other vss r25 power/other vss r26 power/other vss r27 power/other vss r28 power/other vss r29 power/other vss r30 power/other vss r5 power/other vss r7 power/other vss t3 power/other vss t6 power/other vss t7 power/other vss u1 power/other vss u7 power/other vss v23 power/other vss v24 power/other vss v25 power/other vss v26 power/other vss v27 power/other vss v28 power/other vss v29 power/other vss v3 power/other vss v30 power/other vss v6 power/other vss v7 power/other vss w4 power/other vss w7 power/other table 23.alphabetical land assignments land name land # signal buffer type direction vss y2 power/other vss y5 power/other vss y7 power/other vss_mb_ regulation an6 power/other output vss_sense an4 power/other output vssa b23 power/other vtt b25 power/other vtt b26 power/other vtt b27 power/other vtt b28 power/other vtt b29 power/other vtt b30 power/other vtt a25 power/other vtt a26 power/other vtt a27 power/other vtt a28 power/other vtt a29 power/other vtt a30 power/other vtt c25 power/other vtt c26 power/other vtt c27 power/other vtt c28 power/other vtt c29 power/other vtt c30 power/other vtt d25 power/other vtt d26 power/other vtt d27 power/other vtt d28 power/other vtt d29 power/other vtt d30 power/other vtt_out_left j1 power/other output vtt_out_ right aa1 power/other output vtt_sel f27 power/other output vttpwrgd am6 power/other input table 23.alphabetical land assignments land name land # signal buffer type direction
land listing and signal descriptions 54 datasheet table 24.numerical land assignment land # land name signal buffer type direction a2 vss power/other a3 rs2# common clock input a4 d2# source synch input/output a5 d4# source synch input/output a6 vss power/other a7 d7# source synch input/output a8 dbi0# source synch input/output a9 vss power/other a10 d8# source synch input/output a11 d9# source synch input/output a12 vss power/other a13 comp0 power/other input a14 d50# source synch input/output a15 vss power/other a16 dstbn3# source synch input/output a17 d56# source synch input/output a18 vss power/other a19 d61# source synch input/output a20 reserved a21 vss power/other a22 d62# source synch input/output a23 vcca power/other a24 vss power/other a25 vtt power/other a26 vtt power/other a27 vtt power/other a28 vtt power/other a29 vtt power/other a30 vtt power/other b1 vss power/other b2 dbsy# common clock input/output b3 rs0# common clock input b4 d0# source synch input/output b5 vss power/other b6 d5# source synch input/output b7 d6# source synch input/output b8 vss power/other b9 dstbp0# source synch input/output b10 d10# source synch input/output b11 vss power/other b12 d13# source synch input/output b13 reserved b14 vss power/other b15 d53# source synch input/output b16 d55# source synch input/output b17 vss power/other b18 d57# source synch input/output b19 d60# source synch input/output b20 vss power/other b21 d59# source synch input/output b22 d63# source synch input/output b23 vssa power/other b24 vss power/other b25 vtt power/other b26 vtt power/other b27 vtt power/other b28 vtt power/other b29 vtt power/other b30 vtt power/other c1 drdy# common clock input/output c2 bnr# common clock input/output c3 lock# common clock input/output c4 vss power/other c5 d1# source synch input/output c6 d3# source synch input/output c7 vss power/other c8 dstbn0# source synch input/output c9 reserved c10 vss power/other c11 d11# source synch input/output c12 d14# source synch input/output c13 vss power/other c14 d52# source synch input/output c15 d51# source synch input/output c16 vss power/other c17 dstbp3# source synch input/output c18 d54# source synch input/output c19 vss power/other c20 dbi3# source synch input/output c21 d58# source synch input/output table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions datasheet 55 c22 vss power/other c23 vcciopll power/other c24 vss power/other c25 vtt power/other c26 vtt power/other c27 vtt power/other c28 vtt power/other c29 vtt power/other c30 vtt power/other d1 reserved d2 ads# common clock input/output d3 vss power/other d4 hit# common clock input/output d5 vss power/other d6 vss power/other d7 d20# source synch input/output d8 d12# source synch input/output d9 vss power/other d10 d22# source synch input/output d11 d15# source synch input/output d12 vss power/other d13 d25# source synch input/output d14 reserved d15 vss power/other d16 reserved d17 d49# source synch input/output d18 vss power/other d19 dbi2# source synch input/output d20 d48# source synch input/output d21 vss power/other d22 d46# source synch input/output d23 reserved d24 vss power/other d25 vtt power/other d26 vtt power/other d27 vtt power/other d28 vtt power/other d29 vtt power/other d30 vtt power/other e2 vss power/other table 24.numerical land assignment land # land name signal buffer type direction e3 trdy# common clock input e4 hitm# common clock input/output e5 reserved e6 reserved e7 reserved e8 vss power/other e9 d19# source synch input/output e10 d21# source synch input/output e11 vss power/other e12 dstbp1# source synch input/output e13 d26# source synch input/output e14 vss power/other e15 d33# source synch input/output e16 d34# source synch input/output e17 vss power/other e18 d39# source synch input/output e19 d40# source synch input/output e20 vss power/other e21 d42# source synch input/output e22 d45# source synch input/output e23 reserved e24 fc17 power/other output e25 vss power/other e26 vss power/other e27 vss power/other e28 vss power/other e29 vss power/other f2 fc5 common clock input f3 br0# common clock input/output f4 vss power/other f5 rs1# common clock input f6 impsel power/other input f7 vss power/other f8 d17# source synch input/output f9 d18# source synch input/output f10 vss power/other f11 d23# source synch input/output f12 d24# source synch input/output f13 vss power/other f14 d28# source synch input/output table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions 56 datasheet f15 d30# source synch input/output f16 vss power/other f17 d37# source synch input/output f18 d38# source synch input/output f19 vss power/other f20 d41# source synch input/output f21 d43# source synch input/output f22 vss power/other f23 reserved f24 testhi7 power/other input f25 testhi2 power/other input f26 testhi0 power/other input f27 vtt_sel power/other output f28 bclk0 clock input f29 reserved g1 vss power/other g2 fc1 power/other input g3 testhi8 power/other input g4 testhi9 power/other input g5 fc7 source synch output g6 reserved g7 defer# common clock input g8 bpri# common clock input g9 d16# source synch input/output g10 reserved g11 dbi1# source synch input/output g12 dstbn1# source synch input/output g13 d27# source synch input/output g14 d29# source synch input/output g15 d31# source synch input/output g16 d32# source synch input/output g17 d36# source synch input/output g18 d35# source synch input/output g19 dstbp2# source synch input/output g20 dstbn2# source synch input/output g21 d44# source synch input/output g22 d47# source synch input/output g23 reset# common clock input g24 testhi6 power/other input g25 testhi3 power/other input table 24.numerical land assignment land # land name signal buffer type direction g26 testhi5 power/other input g27 testhi4 power/other input g28 bclk1 clock input g29 bsel0 power/other output g30 bsel2 power/other output h1 gtlref0 power/other input h2 gtlref1 power/other input h3 vss power/other h4 rsp# common clock input h5 testhi10 power/other input h6 vss power/other h7 vss power/other h8 vss power/other h9 vss power/other h10 vss power/other h11 vss power/other h12 vss power/other h13 vss power/other h14 vss power/other h15 dp1# common clock input/output h16 dp2# common clock input/output h17 vss power/other h18 vss power/other h19 vss power/other h20 vss power/other h21 vss power/other h22 vss power/other h23 vss power/other h24 vss power/other h25 vss power/other h26 vss power/other h27 vss power/other h28 vss power/other h29 fc15 power/other output h30 bsel1 power/other output j1 vtt_out_left power/other output j2 comp4 power/other input j3 reserved j4 vss power/other j5 req1# source synch input/output table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions datasheet 57 j6 req4# source synch input/output j7 vss power/other j8 vcc power/other j9 vcc power/other j10 vcc power/other j11 vcc power/other j12 vcc power/other j13 vcc power/other j14 vcc power/other j15 vcc power/other j16 dp0# common clock input/output j17 dp3# common clock input/output j18 vcc power/other j19 vcc power/other j20 vcc power/other j21 vcc power/other j22 vcc power/other j23 vcc power/other j24 vcc power/other j25 vcc power/other j26 vcc power/other j27 vcc power/other j28 vcc power/other j29 vcc power/other j30 vcc power/other k1 lint0 asynch gtl+ input k2 vss power/other k3 a20m# asynch gtl+ input k4 req0# source synch input/output k5 vss power/other k6 req3# source synch input/output k7 vss power/other k8 vcc power/other k23 vcc power/other k24 vcc power/other k25 vcc power/other k26 vcc power/other k27 vcc power/other k28 vcc power/other k29 vcc power/other table 24.numerical land assignment land # land name signal buffer type direction k30 vcc power/other l1 lint1 asynch gtl+ input l2 testhi13 asynch gtl+ input l3 vss power/other l4 a6# source synch input/output l5 a3# source synch input/output l6 vss power/other l7 vss power/other l8 vcc power/other l23 vss power/other l24 vss power/other l25 vss power/other l26 vss power/other l27 vss power/other l28 vss power/other l29 vss power/other l30 vss power/other m1 vss power/other m2 thermtrip# asynch gtl+ output m3 stpclk# asynch gtl+ input m4 a7# source synch input/output m5 a5# source synch input/output m6 req2# source synch input/output m7 vss power/other m8 vcc power/other m23 vcc power/other m24 vcc power/other m25 vcc power/other m26 vcc power/other m27 vcc power/other m28 vcc power/other m29 vcc power/other m30 vcc power/other n1 pwrgood power/other input n2 ignne# asynch gtl+ input n3 vss power/other n4 reserved n5 reserved n6 vss power/other n7 vss power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions 58 datasheet n8 vcc power/other n23 vcc power/other n24 vcc power/other n25 vcc power/other n26 vcc power/other n27 vcc power/other n28 vcc power/other n29 vcc power/other n30 vcc power/other p1 testhi11 power/other input p2 smi# asynch gtl+ input p3 init# asynch gtl+ input p4 vss power/other p5 reserved p6 a4# source synch input/output p7 vss power/other p8 vcc power/other p23 vss power/other p24 vss power/other p25 vss power/other p26 vss power/other p27 vss power/other p28 vss power/other p29 vss power/other p30 vss power/other r1 fc2 power/other input r2 vss power/other r3 ferr#/pbe# asynch gtl+ output r4 a8# source synch input/output r5 vss power/other r6 adstb0# source synch input/output r7 vss power/other r8 vcc power/other r23 vss power/other r24 vss power/other r25 vss power/other r26 vss power/other r27 vss power/other r28 vss power/other r29 vss power/other table 24.numerical land assignment land # land name signal buffer type direction r30 vss power/other t1 comp1 power/other input t2 comp5 power/other input t3 vss power/other t4 a11# source synch input/output t5 a9# source synch input/output t6 vss power/other t7 vss power/other t8 vcc power/other t23 vcc power/other t24 vcc power/other t25 vcc power/other t26 vcc power/other t27 vcc power/other t28 vcc power/other t29 vcc power/other t30 vcc power/other u1 vss power/other u2 ap0# common clock input/output u3 ap1# common clock input/output u4 a13# source synch input/output u5 a12# source synch input/output u6 a10# source synch input/output u7 vss power/other u8 vcc power/other u23 vcc power/other u24 vcc power/other u25 vcc power/other u26 vcc power/other u27 vcc power/other u28 vcc power/other u29 vcc power/other u30 vcc power/other v1 msid1 power/other output v2 ll_id0 power/other output v3 vss power/other v4 a15# source synch input/output v5 a14# source synch input/output v6 vss power/other v7 vss power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions datasheet 59 v8 vcc power/other v23 vss power/other v24 vss power/other v25 vss power/other v26 vss power/other v27 vss power/other v28 vss power/other v29 vss power/other v30 vss power/other w1 msid0 power/other output w2 testhi12 power/other input w3 testhi1 power/other input w4 vss power/other w5 a16# source synch input/output w6 a18# source synch input/output w7 vss power/other w8 vcc power/other w23 vcc power/other w24 vcc power/other w25 vcc power/other w26 vcc power/other w27 vcc power/other w28 vcc power/other w29 vcc power/other w30 vcc power/other y1 bootselect power/other input y2 vss power/other y3 reserved y4 a20# source synch input/output y5 vss power/other y6 a19# source synch input/output y7 vss power/other y8 vcc power/other y23 vcc power/other y24 vcc power/other y25 vcc power/other y26 vcc power/other y27 vcc power/other y28 vcc power/other y29 vcc power/other table 24.numerical land assignment land # land name signal buffer type direction y30 vcc power/other aa1 vtt_out_rig ht power/other output aa2 ll_id1 power/other output aa3 vss power/other aa4 a21# source synch input/output aa5 a23# source synch input/output aa6 vss power/other aa7 vss power/other aa8 vcc power/other aa23 vss power/other aa24 vss power/other aa25 vss power/other aa26 vss power/other aa27 vss power/other aa28 vss power/other aa29 vss power/other aa30 vss power/other ab1 vss power/other ab2 ierr# asynch gtl+ output ab3 mcerr# common clock input/output ab4 a26# source synch input/output ab5 a24# source synch input/output ab6 a17# source synch input/output ab7 vss power/other ab8 vcc power/other ab23 vss power/other ab24 vss power/other ab25 vss power/other ab26 vss power/other ab27 vss power/other ab28 vss power/other ab29 vss power/other ab30 vss power/other ac1 tms tap input ac2 dbr# power/other output ac3 vss power/other ac4 reserved ac5 a25# source synch input/output ac6 vss power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions 60 datasheet ac7 vss power/other ac8 vcc power/other ac23 vcc power/other ac24 vcc power/other ac25 vcc power/other ac26 vcc power/other ac27 vcc power/other ac28 vcc power/other ac29 vcc power/other ac30 vcc power/other ad1 tdi tap input ad2 bpm2# common clock input/output ad3 binit# common clock input/output ad4 vss power/other ad5 adstb1# source synch input/output ad6 a22# source synch input/output ad7 vss power/other ad8 vcc power/other ad23 vcc power/other ad24 vcc power/other ad25 vcc power/other ad26 vcc power/other ad27 vcc power/other ad28 vcc power/other ad29 vcc power/other ad30 vcc power/other ae1 tck tap input ae2 vss power/other ae3 reserved ae4 reserved ae5 vss power/other ae6 reserved ae7 vss power/other ae8 sktocc# power/other output ae9 vcc power/other ae10 vss power/other ae11 vcc power/other ae12 vcc power/other ae13 vss power/other ae14 vcc power/other table 24.numerical land assignment land # land name signal buffer type direction ae15 vcc power/other ae16 vss power/other ae17 vss power/other ae18 vcc power/other ae19 vcc power/other ae20 vss power/other ae21 vcc power/other ae22 vcc power/other ae23 vcc power/other ae24 vss power/other ae25 vss power/other ae26 vss power/other ae27 vss power/other ae28 vss power/other ae29 vss power/other ae30 vss power/other af1 tdo tap output af2 bpm4# common clock input/output af3 vss power/other af4 a28# source synch input/output af5 a27# source synch input/output af6 vss power/other af7 vss power/other af8 vcc power/other af9 vcc power/other af10 vss power/other af11 vcc power/other af12 vcc power/other af13 vss power/other af14 vcc power/other af15 vcc power/other af16 vss power/other af17 vss power/other af18 vcc power/other af19 vcc power/other af20 vss power/other af21 vcc power/other af22 vcc power/other af23 vss power/other af24 vss power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions datasheet 61 af25 vss power/other af26 vss power/other af27 vss power/other af28 vss power/other af29 vss power/other af30 vss power/other ag1 trst# tap input ag2 bpm3# common clock input/output ag3 bpm5# common clock input/output ag4 a30# source synch input/output ag5 a31# source synch input/output ag6 a29# source synch input/output ag7 vss power/other ag8 vcc power/other ag9 vcc power/other ag10 vss power/other ag11 vcc power/other ag12 vcc power/other ag13 vss power/other ag14 vcc power/other ag15 vcc power/other ag16 vss power/other ag17 vss power/other ag18 vcc power/other ag19 vcc power/other ag20 vss power/other ag21 vcc power/other ag22 vcc power/other ag23 vss power/other ag24 vss power/other ag25 vcc power/other ag26 vcc power/other ag27 vcc power/other ag28 vcc power/other ag29 vcc power/other ag30 vcc power/other ah1 vss power/other ah2 reserved ah3 vss power/other ah4 a32# source synch input/output table 24.numerical land assignment land # land name signal buffer type direction ah5 a33# source synch input/output ah6 vss power/other ah7 vss power/other ah8 vcc power/other ah9 vcc power/other ah10 vss power/other ah11 vcc power/other ah12 vcc power/other ah13 vss power/other ah14 vcc power/other ah15 vcc power/other ah16 vss power/other ah17 vss power/other ah18 vcc power/other ah19 vcc power/other ah20 vss power/other ah21 vcc power/other ah22 vcc power/other ah23 vss power/other ah24 vss power/other ah25 vcc power/other ah26 vcc power/other ah27 vcc power/other ah28 vcc power/other ah29 vcc power/other ah30 vcc power/other aj1 bpm1# common clock input/output aj2 bpm0# common clock input/output aj3 itp_clk1 tap input aj4 vss power/other aj5 a34# source synch input/output aj6 a35# source synch input/output aj7 vss power/other aj8 vcc power/other aj9 vcc power/other aj10 vss power/other aj11 vcc power/other aj12 vcc power/other aj13 vss power/other aj14 vcc power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions 62 datasheet aj15 vcc power/other aj16 vss power/other aj17 vss power/other aj18 vcc power/other aj19 vcc power/other aj20 vss power/other aj21 vcc power/other aj22 vcc power/other aj23 vss power/other aj24 vss power/other aj25 vcc power/other aj26 vcc power/other aj27 vss power/other aj28 vss power/other aj29 vss power/other aj30 vss power/other ak1 thermdc power/other ak2 vss power/other ak3 itp_clk0 tap input ak4 vid4 power/other output ak5 vss power/other ak6 fc8 ak7 vss power/other ak8 vcc power/other ak9 vcc power/other ak10 vss power/other ak11 vcc power/other ak12 vcc power/other ak13 vss power/other ak14 vcc power/other ak15 vcc power/other ak16 vss power/other ak17 vss power/other ak18 vcc power/other ak19 vcc power/other ak20 vss power/other ak21 vcc power/other ak22 vcc power/other ak23 vss power/other ak24 vss power/other table 24.numerical land assignment land # land name signal buffer type direction ak25 vcc power/other ak26 vcc power/other ak27 vss power/other ak28 vss power/other ak29 vss power/other ak30 vss power/other al1 thermda power/other al2 prochot# asynch gtl+ input/output al3 vss power/other al4 vid5 power/other output al5 vid1 power/other output al6 vid3 power/other output al7 vss power/other al8 vcc power/other al9 vcc power/other al10 vss power/other al11 vcc power/other al12 vcc power/other al13 vss power/other al14 vcc power/other al15 vcc power/other al16 vss power/other al17 vss power/other al18 vcc power/other al19 vcc power/other al20 vss power/other al21 vcc power/other al22 vcc power/other al23 vss power/other al24 vss power/other al25 vcc power/other al26 vcc power/other al27 vss power/other al28 vss power/other al29 vcc power/other al30 vcc power/other am1 vss power/other am2 vid0 power/other output am3 vid2 power/other output am4 vss power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions datasheet 63 am5 fc11 power/other output am6 vttpwrgd power/other input am7 fc12 power/other output am8 vcc power/other am9 vcc power/other am10 vss power/other am11 vcc power/other am12 vcc power/other am13 vss power/other am14 vcc power/other am15 vcc power/other am16 vss power/other am17 vss power/other am18 vcc power/other am19 vcc power/other am20 vss power/other am21 vcc power/other am22 vcc power/other am23 vss power/other am24 vss power/other am25 vcc power/other am26 vcc power/other am27 vss power/other am28 vss power/other am29 vcc power/other am30 vcc power/other an1 vss power/other an2 vss power/other an3 vcc_sense power/other output an4 vss_sense power/other output an5 vcc_mb_ regulation power/other output an6 vss_mb_ regulation power/other output an7 fc16 power/other output an8 vcc power/other an9 vcc power/other an10 vss power/other an11 vcc power/other table 24.numerical land assignment land # land name signal buffer type direction an12 vcc power/other an13 vss power/other an14 vcc power/other an15 vcc power/other an16 vss power/other an17 vss power/other an18 vcc power/other an19 vcc power/other an20 vss power/other an21 vcc power/other an22 vcc power/other an23 vss power/other an24 vss power/other an25 vcc power/other an26 vcc power/other an27 vss power/other an28 vss power/other an29 vcc power/other an30 vcc power/other table 24.numerical land assignment land # land name signal buffer type direction
land listing and signal descriptions 64 datasheet 4.2 alphabetical signals reference table 25. signal description (sheet 1 of 9) name type description a[35:3]# input/ output a[35:3]# (address) define a 2 36 -byte physical memory address space. in sub-phase 1 of the address phase, these signals transmit the address of a transaction. in su b-phase 2, these signals transmit transaction type information. these signals must connect the appropriate pins/lands of all agents on the processor fsb. a[35:3]# are protected by parity signals ap[1:0]#. a[35:3]# are source synchronous signals and are latche d into the receiving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processor samples a subset of the a[35:3]# signals to determine power-on configuration. see section 6.1 for more details. a20m# input if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) be fore looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap- around at the 1-mb boundary. asse rtion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assert ion of the corresponding input/ output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# and req[4:0]# signals. all bus agents observe the ads# activati on to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latc h a[35:3]# and req[4:0]# on their rising and falling edges. strobes are associated with signals as shown below. ap[1:0]# input/ output ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[35:3]#, and the transaction type on the req[4:0]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the approp riate pins/lands of all processor fsb agents. the following table defi nes the coverage model of these signals. signals associated strobe req[4:0]#, a[16:3]# adstb0# a[35:17]# adstb1# request signals subphase 1 subphase 2 a[35:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0#
datasheet 65 land listing and signal descriptions bclk[1:0] input the differential pair bclk (bus clock) determines the fsb frequency. all processor fsb agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of bclk0 crossing v cross . binit# input/ output binit# (bus initialization) may be observed and driven by all processor fsb agents and if used , must connect the appropriate pins/lands of all such agents. if th e binit# driver is enabled during power-on configuration, binit# is asserted to signal any bus condition that prevents re liable future operation. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, symmetric agents reset their bus lock# activity and bus request ar bitration state machines. the bus agents do not reset their ioq and transaction tracking state machines upon observation of bini t# activation. once the binit# assertion has been observed, the bus agents will re-arbitrate for the fsb and attempt completion of their bus queue and ioq entries. if binit# observation is disabled during power-on configuration, a central agent may handle an assert ion of binit# as appropriate to the error handling archit ecture of the system. bnr# input/ output bnr# (block next request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. during a bus stall, the current bus owner cannot is sue any new transactions. bootselect input this input is required to determin e whether the processor is installed in a platform that supports the ce leron d processor. the processor will not operate if this signal is low. this input has a weak internal pull-up to v tt . bpm[5:0]# input/ output bpm[5:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance . bpm[5:0]# should connect the appropriate pins/lands of all processor fsb agents. bpm4# provides prdy# (probe re ady) functionality for the tap port. prdy# is a processor output used by debug t ools to determine processor debug readiness. bpm5# provides preq# (probe requ est) functionality for the tap port. preq# is used by debug tool s to request debug operation of the processor. these signals do not have on-die termination. refer to section 2.5.2 for termination requirements. bpri# input bpri# (bus priority request) is us ed to arbitrate for ownership of the processor fsb. it must connect the appropriate pins/lands of all processor fsb agents. observing bp ri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases th e bus by de-asserting bpri#. br0# input/ output br0# drives the breq0# signal in the system and is used by the processor to request th e bus. during power-on configuration this signal is sampled to dete rmine the agent id = 0. this signal does not have on -die termination and must be terminated. table 25. signal description (sheet 1 of 9) name type description
land listing and signal descriptions 66 datasheet bsel[2:0] output the bclk[1:0] frequency select signals bsel[2:0] are used to select the processor inpu t clock frequency. ta b l e 1 8 defines the possible combinations of the signals and the frequency associated with each combination. the required freq uency is determined by the processor, chipset and clock synthesizer. all agents must operate at the same frequency. for more in formation about these signals, including termination re commendations refer to chapter 2 . comp[5:4,1:0] analog comp[1:0] must be terminated to v ss on the system board using precision resistors. comp[5:4 ] must be terminated to v tt on the system board using precision resistors. d[63:0]# input/ output d[63:0]# (data) are the data signal s. these signals provide a 64-bit data path between the processor fsb agents, and must connect the appropriate pins/lands on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[ 3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grou ping of data signals to data strobes and dbi#. furthermore, the dbi# signals dete rmine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is active, the corresponding data group is inverted and ther efore sampled active high. dbi[3:0]# input/ output dbi[3:0]# (data bus inversion) are source synchronous and indicate the polarity of the d[63:0]# signals.the dbi[3:0]# signals are activated when the data on the data bus is inverted. if more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular su b-phase for that 16-bit group. table 25. signal description (sheet 1 of 9) name type description quad-pumped signal groups data group dstbn#/dstbp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0] assignment to data bus bus signal data bus signals dbi3# d[63:48]# dbi2# d[47:32]# dbi1# d[31:16]# dbi0# d[15:0]#
datasheet 67 land listing and signal descriptions dbr# output dbr# (debug reset) is used only in processor systems where no debug port is implemente d on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemen ted in the system, dbr# is a no connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the processor fsb to indicate that the data bus is in use. the data bus is released af ter dbsy# is de-asserted. this signal must connect the appropriat e pins/lands on all processor fsb agents. defer# input defer# is asserted by an agent to indicate that a transaction cannot be ensured in-order comp letion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins/lands of all processor fsb agents. dp[3:0]# input/ output dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by th e agent responsible for driving d[63:0]#, and must connect the appropriate pins/lands of all processor fsb agents. drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be de -asserted to insert idle clocks. this signal must connec t the appropriate pins/l ands of all processor fsb agents. dstbn[3:0]# input/ output dstbn[3:0]# are the data strobes used to latch in d[63:0]#. dstbp[3:0]# input/ output dstbp[3:0]# are the data strobes used to latch in d[63:0]#. fcx other fc signals are signals that are avai lable for compatibility with other processors. table 25. signal description (sheet 1 of 9) name type description signals associated strobe d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobe d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
land listing and signal descriptions 68 datasheet ferr#/pbe# output ferr#/pbe# (floating point erro r/pending break event) is a multiplexed signal and its meaning is qualified by stpclk#. when stpclk# is not asserted, ferr#/pbe# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. when stpclk# is not asserted, ferr#/pbe# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms-dos*-type floating-point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. for additional information on the pending break event functionality, including the identification of su pport of the feature and enable/ disable information, refer to volume 3 of the intel architecture software developer's manual and the intel processor identification and the cpuid instruction application note. gtlref[1:0] input gtlref[1:0] determine the signal reference level for gtl+ input signals. gtlref is used by the gtl+ receivers to determine if a signal is a logical 0 or logical 1. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. any fsb agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reassertin g hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ie rr# is usually accompanied by a shutdown transaction on the processor fsb. this transaction may optionally be converted to an exte rnal error signal (e.g., nmi) by system core logic. the processor wi ll keep ierr# asserted until the assertion of reset#. this signal does not have on-die termination. refer to section 2.5.2 for termination requirements. ignne# input ignne# (ignore numeric error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating- point instructions. if ignne# is de-asserted, the processor generates an exception on a noncontr ol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in co ntrol register 0 (cr0) is set. ignne# is an asynchronous signal . however, to ensure recognition of this signal following an input/ou tput write instruction, it must be valid along with the trdy# assert ion of the corresponding input/ output write bus transaction. impsel input impsel input will determine wh ether the processor uses a 50 or 60 buffer. this pin/land must be tied to gnd on 50 platforms and left as nc on 60 platforms. this input has a weak internal pull-up to v tt . table 25. signal description (sheet 1 of 9) name type description
datasheet 69 land listing and signal descriptions init# input init# (initialization), when asserted , resets integer registers inside the processor without affecting its in ternal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchrono us signal and must connect the appropriate pins/lands of all processor fsb agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itp_clk[1:0] input itp_clk[1:0] are copies of bclk that are used only in processor systems where no debug port is im plemented on the system board. itp_clk[1:0] are used as bclk[1 :0] references for a debug port implemented on an interposer. if a debug port is im plemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. lint[1:0] input lint[1:0] (local apic interrupt) must connect the appropriate pins/ lands of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskabl e interrupt. intr and nmi are backward compatible with the signals of those names on the celeron d processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/ intr or lint[1:0]. because the ap ic is enabled by default after reset, operation of these signals as lint[1:0] is the default configuration. ll_id[1:0] output the ll_id[1:0] signals are used to select the correct loadline slope for the processor. ll_id[1:0] = 00 for the celeron d processor. lock# input/ output lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropri ate pins/lands of all processor fsb agents. for a locked sequence of transactions, lock# is asserted from the beginnin g of the first transaction to the end of the last transaction. when the priority agent asserts bp ri# to arbitrate for ownership of the processor fsb, it will wait unt il it observes lo ck# de-asserted. this enables symmetric agents to retain ownership of the processor fsb throughout the bus locked op eration and ensure the atomicity of lock. mcerr# input/ output mcerr# (machine check error) is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor fsb agents. mcerr# assertion conditions are co nfigurable at a system level. assertion options are define d by the foll owing options: ? enabled or disabled. ? asserted, if configured, for in ternal errors along with ierr#. ? asserted, if configured, by the request initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, refer to the ia-32 software developer?s manual, volume 3: system programming guide . table 25. signal description (sheet 1 of 9) name type description
land listing and signal descriptions 70 datasheet msid[1:0] input msid0 is used to indicate to th e processor whether the platform supports 775_vr_config_05b processors. a 775_vr_config_05b processor will only boot if it?s msid0 pin/land is electrically low. a 775_vr_config_05a processor will ignore this input. msid1 must be electrically lo w for the processor to boot. prochot# input/ output as an output, prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit (tcc) has been activated, if enabled. as an inpu t, assertion of prochot# by the system will activate the tcc, if enabled. the tcc will remain active until the system de-asserts prochot#. see section 5.2.3 for more details. pwrgood input pwrgood (power good) is a pr ocessor input. the processor requires this signal to be a clea n indication that the clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. the pwrgood signal must be supplie d to the processor; it is used to protect internal ci rcuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must connect the appropriate pins/ lands of all processor fsb agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb0#. refer to the ap[1:0]# signal description for a details on parity ch ecking of these signals. reset# input asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, re set# must stay active for at least one millisecond after v cc and bclk have reached their proper specifications. on observing active reset#, all fsb agents will de- assert their outputs within two cl ocks. reset# must not be kept asserted for more than 10 ms while pwrgood is asserted. a number of bus signals are samp led at the active-to-inactive transition of reset# for po wer-on configuration. these configuration options are described in the section 6.1 . this signal does not have on -die termination and must be terminated on the system board. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current tr ansaction), and must connect the appr opriate pins/lands of all processor fsb agents. table 25. signal description (sheet 1 of 9) name type description
datasheet 71 land listing and signal descriptions rsp# input rsp# (response parity) is driven by the response agent (the agent responsible for completion of th e current transa ction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect to th e appropriate pins /lands of all processor fsb agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by any agent ensuring correct parity. sktocc# output sktocc# (socket occupied) will be pulled to ground by the processor. system board designers may use this signal to determine if the processor is present. smi# input smi# (system management interrup t) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current stat e and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during th e de-assertion of reset#, the processor will tri-state its outputs. stpclk# input stpclk# (stop clock), when asse rted, causes the processor to enter a low power stop-g rant state. the processor issues a stop- grant acknowledge transaction, an d stops providing internal clock signals to all processor core units except the fsb and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk# is de-asserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an as ynchronous input. tck input tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi[13:0] input testhi[13:0] must be connected to the processor?s appropriate power source (refer to vtt_out_left and vtt_out_right signal description) through a resistor for proper processor operation. see section 2.4 for more details. thermda other thermal diode anode. see section 5.2.6 . thermdc other thermal diode cathode. see section 5.2.6 . table 25. signal description (sheet 1 of 9) name type description
land listing and signal descriptions 72 datasheet thermtrip# output in the event of a catastrophic c ooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 c above the maximum t c . assertion of thermtrip# (thermal trip) indi cates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. upon assertio n of thermtrip#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. to protect the processor, its core voltage (v cc ) must be removed following the assertion of thermtrip#. driving of the thermtrip# signal is enabled within 10 s of the assertion of pwrgood and is disabled on de-assertion of pwrgood. once activated, thermtrip# remains latched until pwrgood is de-asserted. while the de- assertion of the pwrgood signal will de-assert thermtrip#, if the processor?s junction temperature rema ins at or above the trip level, thermtrip# will again be asserted within 10 s of the assertion of pwrgood. tms input tms (test mode select) is a jtag specification support signal used by debug tools. trdy# input trdy# (target ready) is as serted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appr opriate pins/lands of all fsb agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. vcc input vcc are the power lands for the pr ocessor. the voltage supplied to these lands is determined by the vid[5:0] lands. vcca input vcca provides isolated power for the internal processor core plls. vcciopll input vcciopll provides isolated power for internal processor fsb plls. vcc_sense output vcc_sense is an isolated low im pedance connection to processor core power (v cc ). it can be used to sense or measure voltage near the silicon with little noise. vcc_mb_ regulation output this land is provided as a voltag e regulator feedback sense point for v cc . it is connected internally in the processor package to the sense point land u27 as described in the voltage regulator-down (vrd) 10.1 design guide for desktop socket 775 . vid[5:0] output vid[5:0] (voltage id) signals are used to support automatic selection of power supply voltages (v cc ). refer to the voltage regulator-down (vrd) 10.1 design guide for desktop socket 775 for more information. the voltage supply for these signals must be valid before the vr can supply v cc to the processor. conversely, the vr output must be disabled un til the voltage supply for the vid signals becomes valid. the vid si gnals are needed to support the processor voltage specif ication vari ations. see ta b l e 2 for definitions of these signals. the vr must su pply the voltage that is requested by the signals, or disable itself. vss input vss are the ground lands for the pr ocessor and should be connected to the system ground plane. vssa input vssa is the isolated ground for internal plls. vss_sense output vss_sense is an isolated low impedance connection to processor core v ss . it can be used to sense or measure ground near the silicon with little noise. table 25. signal description (sheet 1 of 9) name type description
datasheet 73 land listing and signal descriptions vss_mb_ regulation output this land is provided as a voltage regulator feedback sense point for v ss . it is connected internally in the processor package to the sense point land v27 as described in the voltage regulator-down (vrd) 10.1 design guide for desktop socket 775 . vtt miscellaneous voltage supply. vtt_out_left vtt_out_right output the vtt_out_left and vtt_out_ri ght signals are included to provide a voltage supply for some si gnals that require termination to v tt on the motherboard. vtt_sel output the vtt_sel signal is used to select the correct v tt voltage level for the processor. vttpwrgd input the processor requires this in put to determine that the v tt voltages are stable and within specification. table 25. signal description (sheet 1 of 9) name type description
land listing and signal descriptions 74 datasheet
datasheet 75 thermal specifications and design considerations 5 thermal specifications and design considerations 5.1 processor thermal specifications the celeron d processor requires a thermal solution to maintain temperatures within the operating limits as set forth in section 5.1.1 . any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the sy stem. as processor technology changes, thermal management becomes increasingly crucial when building computer systems. maintaining the proper thermal environmen t is key to reliable, long-term system operation. a complete thermal solution includes bo th component and system level thermal management features. component level thermal solutions can include active or passive heatsinks attached to the processor integrat ed heat spreader (ihs). typical system level thermal solutions may consist of system fans combined with ducting and venting. for more information on designing a component level thermal solution, refer to the intel ? pentium ? d processor, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines . note: the boxed processor will ship with a component thermal solution. refer to chapter 7 for details on the boxed processor. 5.1.1 thermal specifications to allow for the optimal operation and long-term reliability of intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (t c ) specifications when operating at or below the thermal design power (tdp) value listed per frequency in ta b l e 2 6 . thermal solutions not designed to provide this level of thermal capability may affect the long-term re liability of the processor and system. for more details on thermal solution design, refer to the intel ? pentium ? d processor, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines . the celeron d processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. selection of the appropriate fan speed will be based on the temperature reported by the processor?s thermal diode. if the diode temperature is greater than or equal to t control then the processor case temperature must remain at or below the temperature as specified by the thermal prof ile. if the diode temperature is less than t control then the case temperature is permitte d to exceed the thermal profile, but the diode temperature must remain at or below t control . systems that implement fan speed control must be designed to take these conditions in to account. systems that do not alter the fan speed only need to ensu re the case temperature meets the thermal profile specifications. to determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. intel has developed a methodology for accurate power measurement that correlates to intel test temperature and voltage conditions. refer to the intel ? pentium ? d processor, intel ?
thermal specifications and design considerations 76 datasheet pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines and the processor power characterization methodology for the details of this methodology. the case temperature is defined at the geometric top center of the processor. analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the thermal design power (tdp) indicated in ta b l e 2 6 instead of the maximum processor po wer consumption. the thermal monitor feature is designed to protect the processo r in the unlikely event that an application exceeds the tdp recommendation for a sustaine d periods of time. for more details on the usage of this feature, refer to section 5.2 . in all cases the thermal monitor feature must be enabled for the proces sor to remain within specification. table 26. processor thermal specificatio ns for 775_vr_con fig_05a processors processor number core frequency (ghz) thermal design power (w) minimum t c (c) maximum t c (c) notes 356 3.33 86 5 see ta b l e 2 8 and figure 12 1, 2 notes: 1. thermal design power (tdp) should be used for processor thermal solution design targets. the tdp is not the maximum power that the processor can dissipate. 2. this table shows the maximum tdp for a given frequenc y range. individual processors may have a lower tdp. therefore, the maximum t c will vary depending on the tdp of the individual processor. refer to thermal profile figure and associated table for the allowed combinations of power and t c . 352 3.2 86 5 1 , 2 table 27. processor thermal specificatio ns for 775_vr_con fig_06 processors processor number core frequency (ghz) thermal design power (w) minimum t c (c) maximum t c (c) notes 360 3.46 65 5 see table 28 and figure 13 1, 2 notes: 1. thermal design power (tdp) should be us ed for processor thermal solution design tar gets. the tdp is not the maximum power that the processor can dissipate. 2. this table shows the maximum tdp for a given frequency range. individual processors may have a lower tdp. therefore, the max- imum t c will vary depending on the tdp of the individual processor. refer to thermal profile figure and associated table for the allowed combinations of power and t c .
datasheet 77 thermal specifications and design considerations table 28. thermal profile for 775_vr_config_05a processors power (w) maximum tc (c) power (w) maximum tc (c) power (w) maximum tc (c) power (w) maximum tc (c) 044.32250.74457.16663.4 244.92451.34657.66864.0 445.52651.84858.27064.6 646.02852.45058.87265.2 846.63053.05259.47465.8 10 47.2 32 53.6 54 60.0 76 66.3 12 47.8 34 54.2 56 60.5 78 66.9 14 48.4 36 54.7 58 61.1 80 67.5 16 48.9 38 55.3 60 61.7 82 68.1 18 49.5 40 55.9 62 62.3 84 68.7 20 50.1 42 56.5 64 62.9 86 69.2 figure 12. thermal profile for 775_vr_config_05a processors y = 0.29x + 44.3 40.0 45.0 50.0 55.0 60.0 65.0 70.0 0 1020304050607080 power (w) tcase (c)
thermal specifications and design considerations 78 datasheet table 5-1. thermal profile for 775_vr_config_06 processors power (w) maximum tc (c) power (w) maximum tc (c) 0 43.6 34 54.5 2 44.2 36 55.1 4 44.9 38 55.8 6 45.5 40 56.4 8 46.2 42 57.0 10 46.8 44 57.7 12 47.4 46 58.3 14 48.1 48 59.0 16 48.7 50 59.6 18 49.4 52 60.2 20 50.0 54 60.9 22 50.6 56 61.5 24 51.3 58 62.2 26 51.9 60 62.8 28 52.6 62 63.4 30 53.2 64 64.1 32 53.8 figure 13. thermal profile fo r 775_vr_config_ 06 processors y = 0.32x + 43.6 40.0 45.0 50.0 55.0 60.0 65.0 70.0 0 1020304050607080 power (w) tcase (c)
datasheet 79 thermal specifications and design considerations 5.1.2 thermal metrology the maximum and minimum case temperatures (t c ) for the celeron d processor is specified in ta b l e 2 6 . this temperature specification is meant to help ensure proper operation of the processor. figure 14 illustrates where intel recommends t c thermal measurements should be made. for detaile d guidelines on temperature measurement methodology, refer to the intel ? pentium ? d processor, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines . 5.2 processor thermal features 5.2.1 thermal monitor the thermal monitor feature helps control th e processor temperature by activating the thermal control circuit (tcc) when the processor silicon reaches its maximum operating temperature. the tcc reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. the thermal monitor feature must be enabled for the processor to be operating within specifications. the temperature at which thermal monitor activates the thermal control circuit is not user configurable and is not software visible. bus traffic is snooped in the normal manner, and interrupt requests are latched (and servic ed during the time that the clocks are on) while the tcc is active. when the thermal monitor feature is enabled, and a high temperature situation exists (i.e., tcc is active), the clocks will be mo dulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30?50%). clocks often will not be off for more than 3.0 microseconds when the tcc is active. cycle times are processor speed dependent and will decrease as processor core frequencies increase. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near its maximum operating temperature. once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the tcc goes inactive and clock modulation ceases. figure 14. case temperature (t c ) measurement location 37.5 mm measure t c at this point (geo metric center o f the package) 37.5 mm 37.5 mm measure t c at this point (geo metric center o f the package) 37.5 mm
thermal specifications and design considerations 80 datasheet with a properly designed and characterized thermal solution, it is anticipated that the tcc would only be activated for very shor t periods of time when running the most power intensive applications. the processo r performance impact due to these brief periods of tcc activation is expected to be so minor that it would be immeasurable. an under-designed thermal solution that is not ab le to prevent excessive activation of the tcc in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a t c that exceeds the specified maximum temperature and may affect the long-term reliability of th e processor. in addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the tcc is active continuously. refer to the intel ? pentium ? d processor, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines for information on designing a thermal solution. the duty cycle for the tcc, when activated by the thermal monitor, is factory configured and cannot be modified. the thermal monitor does not require any additional hardware, software drivers, or interrupt handling routines. 5.2.2 on-demand mode the celeron d processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. this mechanism is referred to as ?on-demand? mode and is distinct from the thermal monitor feature. on-demand mode is intended as a means to reduce system level power consumption. systems using the celeron d processor must not rely on software usage of this mechanism to limit the processor temperature. if bit 4 of the acpi p_cnt control register (located in the processor ia32_therm_control msr) is written to a '1 ', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. when using on-demand mode, the duty cycle of the clock modulation is programma ble via bits 3:1 of the same acpi p_cnt control register. in on-demand mode, the duty cycle can be programmed from 12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used in conjunction with the thermal monitor. if the system tries to enable on-demand mode at the same time the tcc is engaged, the factory configured duty cycle of the tcc will override the duty cycle selected by the on-demand mode.
datasheet 81 thermal specifications and design considerations 5.2.3 prochot# signal an external signal, prochot# (processor hot), is asserted when the processor die temperature has reached its maximum operat ing temperature. if the thermal monitor is enabled (note that the thermal monitor must be enabled for the processor to be operating within specification), the tcc will be active when prochot# is asserted. the processor can be configured to generate an interrupt upon the assertion or de- assertion of prochot#. refer to the intel architecture software developer's manuals for specific register and programming details. the celeron d processor implements a bi-directional prochot# capability to allow system designs to protect various components from over-temperature situations. the prochot# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the tcc. the ability to activate the tcc via prochot# can provide a means for thermal protection of system components. one application is the thermal protection of voltage regulators (vr). system designers can create a circuit to monitor the vr temperature and activate the tcc when the temperature limit of the vr is reached. by asserting prochot# (pulled-low) and activating the tcc, the vr can cool down as a result of reduced processor power consumption. bi-directional prochot# can allow vr thermal designs to target maximum sustained current instead of maxi mum current. systems should still provide proper cooling for the vr, and rely on bi-d irectional prochot# only as a backup in case of system cooling failure. refer to th e applicable platform design guide and the voltage regulator-down (vrd) 10.1 design guide for desktop and transportable lga775 socket for details on implementing the bi-directional prochot# feature. 5.2.4 thermtrip# signal regardless of whether or not thermal monitor is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the thermtrip# definition in ta b l e 2 5 ). at this point, the fsb signal thermtrip# will go active and stay active as described in ta b l e 2 5 . thermtrip# activation is independent of processor activity and does not generate any bus cycles. 5.2.5 t control and fan speed reduction t control is a temperature specification based on a temperature reading from the thermal diode. the value for t control will be calibrated in manufacturing and configured for each processor. when t diode is above t control then t c must be at or below t c_max as defined by the thermal profile in ta b l e 2 8 ; otherwise, the processor temperature can be maintained at t control (or lower) as measured by the thermal diode. the purpose of this feature is to suppor t acoustic optimization through fan speed control. contact your field representative for further details. 5.2.6 thermal diode the processor incorporates an on-die pnp transistor whose base emitter junction is used as a thermal "diode", with its collector shorted to ground. a thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. ta b l e 2 9 , ta b l e 3 0 , ta b l e 3 1 , and ta b l e 3 2 provide the "diode" parameter and interface sp ecifications. two different sets of "diode" parameters are listed in ta b l e 2 9 and 30 . the diode model parameters ( ta b l e 2 9 ) apply to traditional thermal sensors that use the diode equation to determine the processor
thermal specifications and design considerations 82 datasheet temperature. transistor model parameters ( ta b l e 3 0 ) have been added to support thermal sensors that use the transistor equation method. the transistor model may provide more accurate temperature measurem ents when the diode ideality factor is closer to the maximum or minimum limits. this thermal "diode" is separate from the thermal monitor's thermal sensor and cannot be used to predict the behavior of the thermal monitor. notes: 1. intel does not support or re commend operation of the thermal diode under reverse bias. 2. characterized across a temperature range of 50 - 80 c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by the diode equation: i fw = i s * (e qv d /nkt ?1) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). 5. the series resistance, r t , is provided to allow for a mo re accurate measurement of the junction temperature. r t , as defined, includes the land s of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. rt ca n be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. another application is that a temperat ure offset can be manually calculated and programmed into an offset register in the remote diode ther mal sensors as exemplified by the equation: t error = [r t * (n-1) * i fwmin ] / [nk/q * ln n] where t error = sensor temperature error, n = sensor curre nt ratio, k = boltzmann constant, q = electronic charge. notes: 1. intel does not support or re commend operation of the thermal diode under reverse bias. 2. same as i fw in ta b l e 2 9 3. characterized across a temperature range of 50 ? 80 c. 4. not 100% tested. specified by design characterization. 5. the ideality factor, nq, represents the deviat ion from ideal transistor model behavior as exemplified by the equation for the collector current: i c = i s * (e qv be /n q kt ?1) where i s = saturation current, q = electronic charge, v be = voltage across the trans istor base emitter junction (same nodes as vd), k = boltzmann constant, and t = absolute temperature (kelvin). 6. the series resistance, r t, provided in the diode model table ( ta b l e 2 9 ) can be used for more accurate readings as needed. table 29. thermal ?diode? pa rameters using diode model symbol parameter min typ max unit notes i fw forward bias current 5 ? 200 a 1 n diode ideality factor 1.000 1.009 1.050 - 2, 3, 4 r t series resistance 2.79 4.52 6.24 2, 3, 5 table 30. thermal ?diode? parame ters using transistor model symbol parameter min typ max unit notes i fw forward bias current 5 ? 200 a 1, 2 i e emitter current 5 ? 200 a n q transistor ideality 0.997 1.001 1.005 3, 4, 5 beta 0.391 ? 0.760 3, 4 r t series resistance 2.79 4.52 6.24 3, 6
datasheet 83 thermal specifications and design considerations when calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. calculating the temperature is then accomplished using the equations listed under ta b l e 2 9 . in most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. if the designer of the temperature sensing device assumes a perfect diode the ideality value (also called n trim ) will be 1.000. given that most diodes are not perfect, the designers usually select a n trim value that more closely matches the behavior of the diodes in the processor. if the processors diode ideality deviates from that of n trim , each calculated temperature will be offset by a fixed amount. this temperature offset can be calculated with the equation: t error(nf) = t measured x (1 ? n actual /n trim ) where t error(nf) is the offset in degrees c, t measured is in kelvin, n actual is the measured ideality of the diode, and n trim is the diode ideality assumed by the temperature sensing device. to improve the accuracy of diode based temperature measurements, a new register containing thermal diode offset data has been added to the celeron d processor. during manufacturing, each processors thermal diode will be evaluated for its behavior relative to a theoretical diode. using the eq uation above, the temperature error created by the difference between n trim and the actual ideality of the particular processor will be calculated. this thermal diode offset valu e will be programmed in to the new diode correction msr and when added to the thermal diode base value can be used to correct temperatures read by diode based temperature sensing devices. if the n trim value used to calculate the thermal diode offset differs from the n trim value used in a temperature sensing device, the t error(nf) may not be accurate. if desired, the thermal diode offset can be adjusted by calculating n actual and then recalculating the offset using the actual n trim as defined in the temperature sensor manufacturers' datasheet. the diode_base value and n trim used to calculate the diode_correction_offset are listed in ta b l e 3 1 . table 31. thermal ?diode? n trim and diode_correction_offset symbol parameter unit n trim diode ideality used to calculate diode_offset 1.008 diode_base diode base 0 c table 32. thermal diode interface signal name land numb er signal description thermda al1 diode anode thermdc ak1 diode cathode
thermal specifications and design considerations 84 datasheet
datasheet 85 features 6 features 6.1 power-on configuration options several configuration options can be configured by hardware. the celeron d processor samples the hardware configuration at reset, on the active-to-inactive transition of reset#. for specifications on these options, refer to ta b l e 3 3 . the sampled information configures the processor for subsequent operation. these configuration options cannot be changed except by another reset. all resets reconfigure the processor; for reset purposes, the pr ocessor does not distinguish between a "warm" reset and a "power-on" reset. 6.2 clock control and low power states the processor allows the use of autohalt and stop-grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 15 for a visual representation of the processor low power states. table 33. power-on configuration option signals configuration option signal 1 , 2 notes: 1. asserting this signal du ring reset# will select the corresponding option. 2. address signals not identified in this ta ble as configuration options should not be asserted during reset#. output tristate smi# execute bist init# in order queue pipelining (set ioq depth to 1) a7# disable mcerr# observation a9# disable binit# observation a10# apic cluster id (0-3) a[12:11]# disable bus parking a15# symmetric agent arbitration id br0# reserved a[6:3]#, a8#, a[14:13]#, a[16:35]#
features 86 datasheet 6.2.1 normal state this is the normal operating state for the processor. 6.2.2 halt and enhanced halt powerdown states the celeron d processor supports the halt or enhanced halt powerdown state. the enhanced halt powerdown state is conf igured and enabled via the bios. the enhanced halt state must be enabled via the bios for the processor to remain within its specifications. the enhanced halt state is a lower power state as compared to the stop grant state. if enhanced halt is not enabled, the de fault powerdown state entered will be halt. refer to the following sections for details about the halt and enhanced halt states. figure 15. processor low power state machine enhanced halt or halt state bclk running snoops and interrupts allowed normal state normal execution enhanced halt snoop or halt snoop state bclk running service snoops to caches stop grant state bclk running snoops and interrupts allowed snoop event occurs snoop event serviced init#, binit#, intr, nmi, smi#, reset#, fsb interrupts stpclk# asserted stpclk# de-asserted s t pcl k # asse rt ed stp clk # d e - a sse r te d snoop event occurs snoop event serviced halt or mwait instruction and halt bus cycle generated stop grant snoop state bclk running service snoops to caches
datasheet 87 features 6.2.2.1 halt powerdown state halt is a low power state entered when all the logical processors have executed the halt or mwait instructions. when one of the logical processors executes the halt instruction, that logical processor is halted, however, the other processor continues normal operation. the processor will transiti on to the normal state upon the occurrence of smi#, binit#, init#, or lint[1:0] (nmi, intr). reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the halt power down state. see the intel architecture software developer's manual, volume iii: system programmer's guide for more information. the return from a system management interrupt (smi) handler can be to either normal mode or the halt power down state. see the intel architecture software developer's manual, volume iii: system programmer's guide for more information. the system can generate a stpclk# while th e processor is in the halt power down state. when the system de-asserts the st pclk# interrupt, the processor will return execution to the halt state. while in halt power down state, the processor will process bus snoops. 6.2.2.2 enhanced halt powerdown state enhanced halt is a low power state entered when all logical processors have executed the halt or mwait instructions and enhanc ed halt has been enabled via the bios. when one of the logical processors executes the halt instruction, that logical processor is halted; however, the other processor continues normal operation. the processor will automatically transition to a lower frequency and voltage operating point before entering the enhanced halt st ate. note that the processor fsb frequency is not altered; only the internal core fr equency is changed. when entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower vid. while in enhanced halt state, th e processor will process bus snoops. the processor exits the enhanced halt st ate when a break event occurs. when the processor exits the enhanced halt state, it will first transition the vid to the original value and then change the bus ratio back to the original value. 6.2.3 stop grant state when the stpclk# signal is asserted, the stop grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued stop grant acknowledge special bus cycle. since the gtl+ signals receive power from the fsb, these signals should not be driven (allowing the level to return to v tt ) for minimum power drawn by the termination resistors in this state. in addition, all other input signals on the fsb should be driven to the inactive state. binit# will not be serviced while the processor is in stop grant state. the event will be latched and can be serviced by software upon exit from the stop grant state. reset# will cause the processor to immediatel y initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the de- assertion of the stpclk# signal. a transition to the grant snoop state will occur when the processor detects a snoop on the fsb (see section 6.2.4 ).
features 88 datasheet while in the stop-grant state, smi#, init#, binit# and lint[1:0] will be latched by the processor, and only serviced when the pr ocessor returns to the normal state. only one occurrence of each event will be recogn ized upon return to the normal state. while in stop-grant state, the processor will process a fsb snoop. 6.2.4 enhanced halt snoop or halt snoop state, stop grant snoop state the enhanced halt snoop state is used in conjunction with the new enhanced halt state. if enhanced halt state is not en abled in the bios, the default snoop state entered will be the halt snoop state. refer to the sections below for details on halt snoop state, grant snoop state and enhanced halt snoop state. 6.2.4.1 halt snoop state, stop grant snoop state the processor will respond to snoop transactio ns on the fsb while in stop-grant state or in halt power down state. during a sn oop transaction, the processor enters the halt snoop state:stop grant snoop state. the processor will stay in this state until the snoop on the fsb has been serviced (whether by the processor or another agent on the fsb). after the snoop is serviced, the proce ssor will return to the stop grant state or halt power down state, as appropriate. 6.2.4.2 enhanced halt snoop state the enhanced halt snoop state is the defa ult snoop state when the enhanced halt state is enabled via the bios. the processor will remain in the lower bus ratio and vid operating point of the enhanced halt state. while in the enhanced halt snoop state, snoops are handled the same way as in the halt snoop state. after the snoop is serviced the processor will return to the enhanced halt state.
datasheet 89 boxed processor specifications 7 boxed processor specifications the celeron d processor will also be offered as an intel boxed processor. intel boxed processors are intended for system integrat ors who build systems from baseboards and standard components. the boxed celeron d processor will be supplied with a cooling solution. this chapter documents baseboard and system requirements for the cooling solution that will be supplied with the bo xed celeron d processor. this chapter is particularly important for oems that manufac ture baseboards for system integrators. unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. figure 16 shows a mechanical representation of a boxed celeron d processor. note: ? drawings in this section reflect only the specifications on the intel boxed processor product. these dimensions should not be used as a generic keep-out zone for all cooling solutions. it is the system designers? responsibility to consider their proprietary cooling solution when designing to the required keep -out zone on their system platforms and chassis. refer to the intel ? pentium ? d processor, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines for further guidance. contact your local intel sales representative for this document. note: the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. 7.1 mechanical specifications 7.1.1 boxed processor coo ling solution dimensions this section documents the mechanical specifications of the boxed celeron d processor. the boxed processor will be shipped with an unattached fan heatsink. figure 16 shows a mechanical representation of the boxed celeron d processor. figure 16. mechanical represen tation of the boxed processor
boxed processor specifications 90 datasheet clearance is required around the fan heatsi nk to ensure unimpeded airflow for proper cooling. the physical space requirements an d dimensions for the boxed processor with assembled fan heatsink are shown in figure 17 (side view), and figure 18 (top view). the airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and syst em designs. airspace requirements are shown in figure 22 and figure 23 . note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning. notes: 1. the boxed celeron d processor in the 775-la nd package cooling solution with clip is currently under development and, at this ti me, is preliminary. the diagrams shown may not reflect the final product. 2. diagram does not show the attached hardware fo r the clip design and is provided only as a mechanical representation. figure 17. space requir ements for the boxed processor (side view: applies to all four side views) figure 18. space requir ements for the boxed processor (top view) 95.0 [3.74] 10.0 [0.39] 25.0 [0.98] 81.3 [3.2] 95.0 [3.74] 95.0 [3.74]
datasheet 91 boxed processor specifications 7.1.2 boxed processor fan heatsink weight the boxed processor fan heatsink will not weigh more than 550 grams. see chapter 5 and the intel ? pentium ? d processor, intel ? pentium ? processor extreme edition, and intel ? pentium ? 4 processor thermal and mechanical design guidelines for details on the processor weight and heatsink requirements. 7.1.3 boxed processor retention mechanism and heatsink attach clip assembly the boxed processor thermal solution requir es a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. the boxed processor will ship with the heatsink attach clip assembly. 7.2 electrical requirements 7.2.1 fan heatsi nk power supply the boxed processor's fan heatsink requires a +12 v power supply. a fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. the power cable connector and pinout are shown in figure 20 . baseboards must provide a matched power header to support the boxed processor. ta b l e 3 4 contains specifications for the input and output signals at the fan heatsink connector. the fan heatsink outputs a sense signal that is an open-collector output that pulses at a rate of two pulses per fan revolution. a baseboard pull-up resistor provides v oh to match the system board-mounted fan speed mo nitor requirements, if applicable. use of the sense signal is optional. if the sense signal is not used, pin 3 of the connector should be tied to gnd. figure 19. space requirements for the boxed processor (overall view)
boxed processor specifications 92 datasheet the fan heatsink receives a pwm signal from the motherboard from the fourth pin of the connector labeled as control. note: the boxed processor?s fan heatsink requires a constant +12 v supplied to pin 2 and does not support variable voltage control or 3-pin pwm control. the power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. the power header identification and location should be documented in the platform documentation, or on the system board itself. figure 21 shows the location of the fan power connector relative to the processor socket. the baseboard power header should be positioned within 4. 33 inches from the center of the processor socket. figure 20. boxed processor fan heatsi nk power cable connector description table 34. fan heatsink power and signal specifications description min typ max unit notes +12 v: 12 volt fan power supply 10.2 12 13.8 v - ic: peak fan current draw fan start-up current draw fan start-up current draw maximum duration ? ? ? 1.1 ? ? 1.5 2.2 1.0 a a second - sense: sense frequency ? 2 ? pulses per fan revolution 1 notes: 1. baseboard should pull this pi n up to 5 v with a resistor. control 21 25 28 khz 2, 3 2. open drain type, pulse width modulated. 3. fan will have a pull-up resistor to 4.75 v, max 5.25 v. pin signal 12 34 1 2 3 4 gnd +12 v sense control straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. match with straight pin, friction lock header on mainboard.
datasheet 93 boxed processor specifications 7.3 thermal specifications this section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.3.1 boxed processor cooling requirements the boxed processor may be directly cooled with a fan heatsink. however, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsib ility of the system integrator. the processor temperature specification is in chapter 5 . the boxed processor fan heatsink is able to keep the processor temperature wi thin the specifications (see ta b l e 2 6 ) in chassis that provide good thermal management. for the boxed processor fan heatsink to operate properly, it is critical that the airflow prov ided to the fan heatsink is unimpeded. airflow of the fan heatsink is into the center and ou t of the sides of the fan heatsink. airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. blocking the airflow to the fan he atsink reduces the cooling efficiency and decreases fan life. figure 22 and figure 23 illustrate an acceptable airspace clearance for the fan heatsink. the air temperature entering the fan should be kept below 38 c. a thermally advantaged chassis with an ai r guide 1.1 is recommended to meet the 38 c requirement. again, meeting the processor's temperature specification is the responsibility of the system integrator. note: the processor fan is the primary source of airflow for cooling the v cc voltage regulator. dedicated voltage regulator cooling components may be necessary if the selected fan is not capable of keeping regulator components below maximum rated temperatures. figure 21. baseboard power header plac ement relative to processor socket b c r110 [4.33]
boxed processor specifications 94 datasheet figure 22. boxed processor fan heatsi nk airspace keep-o ut requirements (side 1 view) figure 23. boxed processor fan heatsi nk airspace keep-o ut requirements (side 2 view)
datasheet 95 debug tools specifications 8 debug tools specifications 8.1 logic analyzer interface (lai) intel is working with two logic analyzer ve ndors to provide logic analyzer interfaces (lais) for use in debugging celeron d processor systems. tektronix and agilent should be contacted to get specific information about their logic analyzer interfaces. the following information is general in nature. sp ecific information must be obtained from the logic analyzer vendor. due to the complexity of celeron d processor systems, the lai is critical in providing the ability to probe and capture fsb signals. there are two sets of considerations to keep in mind when designing a celeron d processor system that can make use of an lai: mechanical and electrical. 8.1.1 mechanical considerations the lai is installed between the processor socket and the celeron d processor. the lai lands plug into the processor socket, while the celeron d processor lands plug into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the celeron d processor and a logic analyzer. the maximum volume occupied by the lai, know n as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstructed inside the system. note that it is possible that the k eepout volume reserved for the lai may differ from the space normally occupied by the ce leron d processor heatsink. if this is the case, the logic analyzer vendor will provide a cooling solution as part of the lai. 8.1.2 electrical considerations the lai will also affect the electrical performanc e of the fsb; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. contact the logic analyzer vendor for electrical specifications and load models for the lai solution it provides.
debug tools specifications 96 datasheet

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